DC/DC layout issues

There are some issues with the DC/DC layout:

• the output cap can be shifted a little to the left for its GND pin to align with the GND pins, then
• for the two top GND pins a GND polygon should be used, tying them to the GND of the output capacitor, to close the (SW pins -> L -> Cout -> GND pins) loop with less inductance;
• the part of the copper pour below the inductor should be removed, it does not serve a purpose and its distance is only 0.5mm from the feedback trace (this should be far from any aggressors, as mentioned in the datasheet);
• for AVIN a trace should be broken out of the PVIN polygon and the AVIN decoupling capacitor should be placed after that trace, next to the pin (now it's placed next to the input decoupling capacitor), to form a small LC filter; and
• less critical (and a schematic issue, not layout) but in the datasheet the SS/TR cap is shown connected to AGND instead of PGND

The datasheet can be consulted for a layout that satisfies all those (p. 28).