- 02 Jul, 2021 3 commits
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The ADC calibration was applying DAC values Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 11 Jun, 2021 4 commits
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Federico Vaga authored
5.0.0 - 2021-06-11 ================== Fixed ----- - sw: concurrent DMA transfers are possible thanks to a wait and retry algorithm - sw: wait 400ms before reading the temperature the first time (the hardware takes time to setup the thermometers) - doc: use cheby files from hdl instead of special implementations
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
On SVEC we can have up to two FMC-ADC-100M mezzanine, potentially triggering at the same time. If such conditions, the driver fails in performing the DMA on both mezzanine because one of the two will fail to request a channel. With this patch we introducte a 10s timeout for the ADC to request a DMA channel on SVEC. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 19 May, 2021 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 11 May, 2021 2 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Tristan Gingold authored
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- 12 Feb, 2021 3 commits
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Federico Vaga authored
5.0.0 - 2021-02-11 ================== Changes ------- - channel sysfs attribute 'chx-offset' does not accept mV (milli-volts) values anymore. Now the unit is uV (micro-Volts) - acquisition sysfs attribute 'decimation' is now named 'undersample' - software trigger is enable by default - on DAC offset saturation set the maximum/minimum value instead of error - the software trigger is not anymore a ZIO attribute. It is now in debugfs Added ----- - multiple trigger sources at the same time - trigger threshold per-channel - channel sysfs attributes to set trigger threshold - sysfs binary attribute to overwrite run-time calibration data - add tool to get/set run-time calibration data - periodically update gain calibration for DAC and ADC - trigger time - MBLT support for SVEC Removed ------- - library is not supported anymore, use adc-lib (https://www.ohwr.org/projects/adc-lib) - fald-acq tool is not supported anymore, use adc-acq from adc-lib (https://www.ohwr.org/projects/adc-lib)
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 11 Feb, 2021 5 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The completion must be initialized everytime Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
As of today the procedures to trigger a DMA transfer for SPEC and SVEC are different, and getting more different with the introduction of the MBLT transfer. So, to improve the readability I decided to clearly split the code in two parts to make visible each procedure. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 10 Feb, 2021 5 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
With the MBLT implementation we can't anymore prepare the memory in advance, and then execute a single DMA transfer for multiple shots. Instead we have to handle sequentially each shot with a dedicated DMA transfer. The previous implementation was relying on the fact that the SVEC DDR offset gets incremented automatically when fetching a word in single transfer mode, and that there is no gap between two consecutive shots. So the transition between a shot and the next one was handled automatically at the FPGA level. The data pre-fetch mechanism in the MBLT implementation increases the throughput. To do this the VME slave core, fetches the next data in DDR in advance, and this moves the DDR offset pointer. At the end of a DMA transfer the DDR offset will not point to the last word, but to some address after it (it depends on the pre-fetch size). For example, a 16 bytes acquisition from DDR offset 0x0000 with pre-fetch 4 bytes will shift the DDR offset register to 0x0014 final DDR offset = initial DDR offset + length + pre-fetch-size 0x0014 = 0x0000 + 0x0010 + 0x0004 This means that in our ADC acquisition we must set again the DDR offset for the following shot (multishot mode), to the address 0x0010. Otherwise the each shot acquisition will be shifted by pre-fetch-size number of bytes. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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Tristan Gingold authored
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- 08 Feb, 2021 4 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 02 Feb, 2021 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 28 Jan, 2021 5 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 05 Jan, 2021 3 commits
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 04 Jan, 2021 2 commits
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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