- 18 Feb, 2019 7 commits
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Federico Vaga authored
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Federico Vaga authored
This program does nothing more than this: dd if=eeprom of=calibration_data ibs=1 skip=256 count=108 obs=108 But it takes the shape of a C program so that we can validate input and we can play with the offset (skip) based on our needs. And we can print them in a more readable format Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Here we do a little hack because I'm already thinking about a future verison of this driver. Instead of providing a calibration binary attribute the driver offers an eeprom_config binary attribute where you can write data as if it was on the eeprom (calibration data included). The driver will extract the calibration and configure the ADC. I'm doing this because we plan to move to platform devices instead of fmc devices. For this reason the access to the eeprom will not be easy as today. To begin with we will have a binary attrbibute where you can write your eeprom content. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Tristan Gingold authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
this patch indroduces an overflow bug: bb859ef7 drv bugfix according to ZIO offset is uV hwval is 32bit, but since user values are now bigger (uV) the multiplication can overflow. We use 64bit to avoid it. Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Signed-off-by: Milosz Malczak <milosz.malczak@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 27 Nov, 2018 2 commits
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Federico Vaga authored
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Federico Vaga authored
the current index variable was not correctly incremented, with the consequence that under certain conditions the return value was wrong. Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Co-Developed: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
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- 22 Oct, 2018 2 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 19 Oct, 2018 3 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 18 Oct, 2018 2 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
We have always been useing an uncalibrated DAC value whenever we were using 'test data' or the input configuration was in open-drain. We recently discovered that this is not true, and actually the voltage range on the input channel is 1V. For this reason the DAC value still needs to be fixed with eeprom calibration data. Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Acked-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
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- 27 Jun, 2018 2 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 26 Feb, 2018 6 commits
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Federico Vaga authored
This prevent to get confused about the value of this register. Whenever the user starts a new acquisition we reset the last triggered register. This guarantee that the value shown comes from the last acquisition Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The driver's users are supposed to use the generic `adc-lib` library from OHWR. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Enabling the software trigger by default it does not cause any harm and it simplifies the code and the interface. The user is free to disable it using the `source` attribute from sysfs. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The gateware version 5 does not have anymore the selection between internal or external trigger. Instead, there is the possibility to have more that one trigger source enabled. Internals: - the acquisition metadata now provides a whiterabbit timestamp and information about the trigger source that started the acquisition Registers change: - one register to enable/disable all trigger sources - one register to set the polarity on all the triggers - threshould/hysteresis for each channel - delay on the following triggers: ext, channel[1; 4] Sysfs changes - add attributes to configure threshould - trigger "enable" will restore the last known enable status
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Federico Vaga authored
In gateware version 5 the logic of the FMC reset bit change from active low to active high: "reset: {1: reset, 0 unreset}". Here with this patch we do a complete reset cycle of the FMC mezzanine. The sleeping time between reset and unreset is huge but we do not care much, this is just the initialization. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 14 Feb, 2018 4 commits
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Federico Vaga authored
In gateware v5 all the necessary compensations are done in FPGA Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The test data from the FPGA does not exercise the FPGA design. With the test data directly from the ADC chip we can use the full ADC design. I decided to evaluate the test mode just before the start of the acquisition in order to be able to change the test pattern at any time. Chaning the test pattern is useful to identify the different acquisitions and being able to validate the acquisition content. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 13 Feb, 2018 4 commits
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Federico Vaga authored
The debugfs is the right place for such output Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
It is good practice to reset thing Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 09 Feb, 2018 1 commit
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Federico Vaga authored
The user-space may not have a definition for `BIT()`, so when an application includes this header it will get error about missing `BIT` definition. This is a fix for this possible of issue. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 29 Jan, 2018 3 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Never used and in v5 it will disappear from the gateware as well Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 21 Dec, 2017 1 commit
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 29 Nov, 2017 1 commit
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 28 Nov, 2017 2 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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