Merge branch '29-automate-convention-version-assignment' into 'master'

Resolve "automate convention version assignment" Closes #29 See merge request be-cem-edl/fec/hardware-modules/fmc-adc-100m14b4cha!18

Merge branch '29-automate-convention-version-assignment' into 'master'
Resolve "automate convention version assignment" Closes #29 See merge request be-cem-edl/fec/hardware-modules/fmc-adc-100m14b4cha!18
f664e0ba · Federico Vaga · cf44c311 · 495222e4 · f664e0ba · 225dd70e
Commit f664e0ba authored Oct 27, 2023 by Federico Vaga
10 changed files
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -12,7 +12,6 @@ include:
    ref: master
    file:
      - 'edl-gitlab-ci.yml'
-  - local: 'hdl/syn/.gitlab-ci.yml'

 cppcheck:
  stage: analyse
@@ -41,3 +40,13 @@ kernel_build_validation:
      if [ "$VMEBRIDGE_BUILDS" != "0" ]; then export CONFIG_VME=n; echo 'VMEBRIDGE did not build successfully. Thus, VME support will not be available.'; else export CONFIG_VME=y; fi
      if [ "$FMC_BUILDS" != "0" ]; then echo 'FMC did not build successfully. Exiting'; exit 1; fi
      if [ "$ZIO_BUILDS" != "0" ]; then echo 'ZIO did not build successfully. Exiting'; exit 1; fi
+
+fpga_synthesis:
+  extends: .synthesis-ise-14-7
+  interruptible: true
+  parallel:
+    matrix:
+      - EDL_CI_SYN_SRC_PATH:
+        - hdl/syn/spec_ref_design_wr
+        - hdl/syn/spec150_ref_design_wr
+        - hdl/syn/svec_ref_design_wr
--- a/general-cores @ 225dd70e
+++ b/general-cores @ 225dd70e
-Subproject commit 1621d6d1f0c3040284136ce4b3b662269d6868d0
+Subproject commit 225dd70e4cf4f93954414916f57ef1366e12e13b
--- a/hdl/syn/.gitlab-ci.yml
+++ b/hdl/syn/.gitlab-ci.yml
-# SPDX-FileCopyrightText: 2022 CERN (home.cern)
-#
-# SPDX-License-Identifier: LGPL-2.1-or-later
-
-variables:
-  _FMC_ADC_BITSTREAM_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/bitstreams
-
-.syn_template: &syn_template
-  interruptible: true
-  stage: build
-  needs: []
-  tags:
-    - xilinx_ise
-    - "14.7"
-  script:
-    - git submodule init && git submodule update
-    - cd hdl/syn/"$SYN_NAME"/
-    - hdlmake
-    - make
-    - |
-      if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
-      then
-        echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
-        exit 1
-      fi
-    - tar -cJf $SYN_NAME.tar.xz *.syr *.par *.twr *.bit *.bin
-    - mkdir -p $_FMC_ADC_BITSTREAM_DEST
-    - cp $SYN_NAME.tar.xz $_FMC_ADC_BITSTREAM_DEST
-  artifacts:
-    name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
-    paths:
-      - $_FMC_ADC_BITSTREAM_DEST/*
-
-SPEC45T synthesis:
-  variables:
-    SYN_NAME: "spec_ref_design_wr"
-  <<: *syn_template
-
-SPEC150T synthesis:
-  variables:
-    SYN_NAME: "spec150_ref_design_wr"
-  <<: *syn_template
-
-SVEC synthesis:
-  variables:
-    SYN_NAME: "svec_ref_design_wr"
-  <<: *syn_template
--- a/hdl/syn/common/.gitignore
+++ b/hdl/syn/common/.gitignore
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+*
+!.gitignore
+!Manifest.py
--- a/hdl/syn/common/Manifest.py
+++ b/hdl/syn/common/Manifest.py
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+
+files = [
+    "sourceid_{}_pkg.vhd".format(syn_top),
+]
+
+try:
+    exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
+         None, {'project': syn_top})
+except Exception as e:
+    print("Error: cannot generate source id file")
+    raise
--- a/hdl/syn/spec150_ref_design_wr/Manifest.py
+++ b/hdl/syn/spec150_ref_design_wr/Manifest.py
@@ -25,6 +25,7 @@ files = [

 modules = {
    "local" : [
+        "../common",
        "../../top/spec_ref_design"
    ],
 }

--- a/hdl/syn/spec_ref_design_wr/Manifest.py
+++ b/hdl/syn/spec_ref_design_wr/Manifest.py
@@ -25,6 +25,7 @@ files = [

 modules = {
    "local" : [
+        "../common",
        "../../top/spec_ref_design"
    ],
 }

--- a/hdl/syn/svec_ref_design_wr/Manifest.py
+++ b/hdl/syn/svec_ref_design_wr/Manifest.py
@@ -30,6 +30,7 @@ files = [

 modules = {
    "local" : [
+        "../common",
        "../../top/svec_ref_design"
    ],
 }

--- a/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
@@ -28,6 +28,7 @@ use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
 use work.fmc_adc_mezzanine_pkg.all;
 use work.wr_board_pkg.all;
+use work.sourceid_spec_ref_fmc_adc_100Ms_pkg;

 entity spec_ref_fmc_adc_100Ms is
  generic(
@@ -394,9 +395,9 @@ begin  -- architecture arch
    generic map (
      g_VENDOR_ID    => x"0000_10DC",
      g_DEVICE_ID    => x"4144_4301", -- "ADC1"
-      g_VERSION      => x"0600_0004",
+      g_VERSION      => sourceid_spec_ref_fmc_adc_100Ms_pkg.version,
      g_CAPABILITIES => x"0000_0000",
-      g_COMMIT_ID    => (others => '0'))
+      g_COMMIT_ID    => sourceid_spec_ref_fmc_adc_100Ms_pkg.sourceid)
    port map (
      clk_i   => clk_sys_62m5,
      rst_n_i => rst_sys_62m5_n,

--- a/hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+++ b/hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
@@ -28,6 +28,7 @@ use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
 use work.fmc_adc_mezzanine_pkg.all;
 use work.wr_board_pkg.all;
+use work.sourceid_svec_ref_fmc_adc_100Ms_pkg;

 entity svec_ref_fmc_adc_100Ms is
  generic(
@@ -476,9 +477,9 @@ begin -- architecture arch
    generic map (
      g_VENDOR_ID    => x"0000_10DC",
      g_DEVICE_ID    => x"4144_4302", -- "ADC2"
-      g_VERSION      => x"0600_0004",
+      g_VERSION      => sourceid_svec_ref_fmc_adc_100Ms_pkg.version,
      g_CAPABILITIES => x"0000_0000",
-      g_COMMIT_ID    => (others => '0'))
+      g_COMMIT_ID    => sourceid_svec_ref_fmc_adc_100Ms_pkg.sourceid)
    port map (
      clk_i   => clk_sys_62m5,
      rst_n_i => rst_sys_62m5_n,