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FMC ADC 100M 14b 4cha
Commit b758e99c authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: automate version assignment

parent cf44c311
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Inline Side-by-side
Showing with 31 additions and 5 deletions
general-cores @ 225dd70e
Subproject commit 1621d6d1f0c3040284136ce4b3b662269d6868d0
Subproject commit 225dd70e4cf4f93954414916f57ef1366e12e13b
hdl/syn/common/.gitignore 0 → 100644
View file @ b758e99c
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
hdl/syn/common/Manifest.py 0 → 100644
View file @ b758e99c
# SPDX-FileCopyrightText: 2023 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
files = [
"sourceid_{}_pkg.vhd".format(syn_top),
]
try:
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': syn_top})
except Exception as e:
print("Error: cannot generate source id file")
raise
hdl/syn/spec150_ref_design_wr/Manifest.py
View file @ b758e99c
......@@ -25,6 +25,7 @@ files = [
modules = {
"local" : [
"../common",
"../../top/spec_ref_design"
],
}
......
hdl/syn/spec_ref_design_wr/Manifest.py
View file @ b758e99c
......@@ -25,6 +25,7 @@ files = [
modules = {
"local" : [
"../common",
"../../top/spec_ref_design"
],
}
......
hdl/syn/svec_ref_design_wr/Manifest.py
View file @ b758e99c
......@@ -30,6 +30,7 @@ files = [
modules = {
"local" : [
"../common",
"../../top/svec_ref_design"
],
}
......
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ b758e99c
......@@ -28,6 +28,7 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.wr_board_pkg.all;
use work.sourceid_spec_ref_fmc_adc_100Ms_pkg;
entity spec_ref_fmc_adc_100Ms is
generic(
......@@ -394,9 +395,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4301", -- "ADC1"
g_VERSION => x"0600_0004",
g_VERSION => sourceid_spec_ref_fmc_adc_100Ms_pkg.version,
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
g_COMMIT_ID => sourceid_spec_ref_fmc_adc_100Ms_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ b758e99c
......@@ -28,6 +28,7 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.wr_board_pkg.all;
use work.sourceid_svec_ref_fmc_adc_100Ms_pkg;
entity svec_ref_fmc_adc_100Ms is
generic(
......@@ -476,9 +477,9 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4302", -- "ADC2"
g_VERSION => x"0600_0004",
g_VERSION => sourceid_svec_ref_fmc_adc_100Ms_pkg.version,
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
g_COMMIT_ID => sourceid_svec_ref_fmc_adc_100Ms_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......
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