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F
FMC ADC 100M 14b 4cha
Commit 200e3529 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: fix SVEC FPGA build

parent b0544ee0
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hdl/syn/svec_ref_design_wr/svec_ref_fmc_adc_100Ms_wr.ucf
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......@@ -175,6 +175,9 @@ NET "gen_fmc_mezzanine[?].*/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 2.0
INST "gen_fmc_mezzanine[0].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X66Y189;
INST "gen_fmc_mezzanine[1].*/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X69Y2;
# Needed for the DDR
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# IOB exceptions
#----------------------------------------
......
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