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EtherBone Core
Commit 2bdca1c9 authored by Mathias Kreider's avatar Mathias Kreider
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Fixed too high padding length in eb_framer 

TODO: Include safeguard against overloading fixed size packets
parent 6dc18040
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Showing with 193 additions and 187 deletions
hdl/eb_master_core/eb_framer.vhd
View file @ 2bdca1c9
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hdl/eb_master_core/eb_master_tb.vhd
View file @ 2bdca1c9
......@@ -42,7 +42,7 @@ ARCHITECTURE behavior OF test_tb IS
signal eop : std_logic;
constant c_RESET : unsigned(31 downto 0) := x"00000000";
constant c_RESET : unsigned(31 downto 0) := x"00200000";
constant c_FLUSH : unsigned(31 downto 0) := c_RESET +4; --wo 04
constant c_STATUS : unsigned(31 downto 0) := c_FLUSH +4; --rw 08
constant c_SRC_MAC_HI : unsigned(31 downto 0) := c_STATUS +4; --rw 0C
......@@ -102,7 +102,8 @@ slave_stall <= master_i.stall;
procedure wb_wr( adr : in unsigned(31 downto 0);
dat : in std_logic_vector(31 downto 0)
dat : in std_logic_vector(31 downto 0);
hold : in std_logic
) is
begin
......@@ -117,7 +118,7 @@ slave_stall <= master_i.stall;
wait for clk_period;
end loop;
master_o.stb <= '0';
master_o.cyc <= '0';
master_o.cyc <= hold;
wait for clk_period;
end procedure wb_wr;
......@@ -186,42 +187,26 @@ slave_stall <= master_i.stall;
rst_n <= '1';
wait until rising_edge(clk);
wb_wr(c_SRC_MAC_HI, x"D15EA5ED");
wb_wr(c_SRC_MAC_LO, x"BEEF0000");
wb_wr(c_SRC_IPV4, x"CAFEBABE");
wb_wr(c_SRC_UDP_PORT, x"0000EBD0");
wb_wr(c_DST_MAC_HI, x"11223344");
wb_wr(c_DST_MAC_LO, x"55660000");
wb_wr(c_DST_IPV4, x"C0A80064");
wb_wr(c_DST_UDP_PORT, x"0000EBD1");
wb_wr(c_OPS_MAX, x"00000010");
wb_wr(c_PAC_LEN, x"00000050");
wb_wr(c_OPA_HI, x"00000000");
wb_wr(c_EB_OPT, x"00000000");
-- hold ops offs adr_inc we send
wb_send_test('0', 1, x"00200000", 4, '0', '1'); -- 3 wr
wb_send_test('0', 1, x"00200000", 4, '1', '1'); -- 3 wr
--wb_send_test('0', 1, x"00000000", 4, '0', '1'); -- 1 rd
--wb_send_test('1', 5, x"00000000", 4, '1', '0'); -- 1 wr
--wb_send_test('0', 1, x"00001100", 4, '0', '0'); -- 1 rd
--wb_send_test('1', 1, x"00000000", 4, '1', '0'); -- 1 wr
--wb_send_test('0', 1, x"00001000", 4, '0', '1'); -- 1 rd
--wb_send_test('1', 1, x"00001000", 4, '1', '0'); -- 1 wr
---wb_send_test('0', 2, x"00001000", 4, '0', '0'); -- 1 rd
--wb_send_test('1', 10, x"00000000", 0, '0', '0'); -- 10 rd
--wb_send_test('0', 10, x"00000000", 4, '0', '0'); -- 10 rd
--wb_send_test('1', 1, x"00000010", 0, '0', '0'); -- 1 rd
---wb_send_test('1', 1, x"00000020", 0, '0', '0'); -- 1 rd
--wb_send_test('1', 1, x"00000030", 0, '0', '0'); -- 1 rd
--wb_send_test('0', 1, x"00000040", 0, '0', '1'); -- 1 rd
wb_wr(c_SRC_MAC_HI, x"D15EA5ED", '1');
wb_wr(c_SRC_MAC_LO, x"BEEF0000", '1');
wb_wr(c_SRC_IPV4, x"CAFEBABE", '1');
wb_wr(c_SRC_UDP_PORT, x"0000EBD0", '1');
wb_wr(c_DST_MAC_HI, x"11223344", '1');
wb_wr(c_DST_MAC_LO, x"55660000", '1');
wb_wr(c_DST_IPV4, x"C0A80064", '1');
wb_wr(c_DST_UDP_PORT, x"0000EBD1", '1');
wb_wr(c_OPS_MAX, x"00000010", '1');
wb_wr(c_PAC_LEN, x"00000050", '1');
wb_wr(c_OPA_HI, x"00000000", '1');
wb_wr(c_EB_OPT, x"00000000", '0');
wb_wr(x"00300000", x"DEADBEE0", '0');
wb_wr(x"00300004", x"DEADBEE1", '0');
wb_wr(x"00380008", x"DEADBEE2", '0');
wb_wr(x"0030000C", x"DEADBEE3", '0');
wb_wr(x"00300010", x"DEADBEE4", '0');
wait for clk_period*500;
wb_wr(c_FLUSH, x"00000001", '0');
wait;
end process;
......
hdl/eb_master_core/eb_master_top.vhd
View file @ 2bdca1c9
......@@ -86,9 +86,9 @@ architecture rtl of eb_master_top is
signal s_narrow2framer : t_wishbone_master_in;
signal s_narrow2tx : t_wishbone_master_out;
signal s_tx2narrow : t_wishbone_master_in;
constant c_dat_bit : natural := t_wishbone_address'length - g_adr_bits_hi+1;
constant c_rw_bit : natural := t_wishbone_address'length - g_adr_bits_hi;
constant c_dat_bit : natural := t_wishbone_address'left - g_adr_bits_hi +2;
constant c_rw_bit : natural := t_wishbone_address'left - g_adr_bits_hi +1;
begin
-- instances:
......@@ -113,12 +113,13 @@ begin
slave_o.rty <= '0';
wbif: eb_master_wb_if
generic map (g_adr_bits_hi => g_adr_bits_hi)
PORT MAP (
clk_i => clk_i,
rst_n_i => rst_n_i,
wb_rst_n_o => wb_rst_n,
flush_o => s_tx_send_now,
flush_o => open,
slave_i => slave_i,
slave_dat_o => s_dat,
......@@ -133,7 +134,7 @@ begin
his_ip_o => s_his_ip,
his_port_o => s_his_port,
length_o => s_length,
max_ops_o => s_max_ops,
adr_hi_o => s_adr_hi,
eb_opt_o => s_cfg_rec_hdr
);
......@@ -155,7 +156,10 @@ begin
-- | Write |
-- |_________|
s_slave_i.cyc <= slave_i.cyc and slave_i.adr(c_dat_bit);
s_tx_send_now <= '1' when slave_i.adr(c_dat_bit) = '0' and slave_i.adr(7 downto 0) = x"04"
else '0';
s_slave_i.cyc <= slave_i.cyc and (slave_i.adr(c_dat_bit) or s_tx_send_now);
s_slave_i.we <= slave_i.adr(c_rw_bit);
s_slave_i.adr <= s_adr_hi(s_adr_hi'left downto s_adr_hi'length-g_adr_bits_hi) & slave_i.adr(slave_i.adr'left-g_adr_bits_hi downto 0);
......
hdl/eb_master_core/eb_master_wb_if.vhd
View file @ 2bdca1c9
......@@ -106,7 +106,7 @@ signal r_busy : std_logic;
signal r_eb_sent : std_logic;
constant c_adr_mask : std_logic_vector(31 downto 0) := not std_logic_vector(to_unsigned(2**(32-g_adr_bits_hi+1)-1, 32));
constant c_dat_bit : natural := 31-g_adr_bits_hi+2;
begin
......@@ -177,7 +177,8 @@ begin
if(push = '1') then
--CTRL REGISTERS
if(slave_i.adr(32-g_adr_bits_hi+1) = '0') then
if(slave_i.adr(c_dat_bit) = '0') then
report "c_dat0";
if(slave_i.we = '1') then
case v_adr is
when c_RESET => r_rst_n <= '0'; r_ack <= '1';
......@@ -194,7 +195,8 @@ begin
when c_OPA_HI => wr(v_adr, c_adr_mask);
when c_OPS_MAX => wr(v_adr);
when c_EB_OPT => wr(v_adr, x"0000FFFF");
when others => r_err <= '1';
when others => report "write to adr in cmd space not mapped";
r_err <= '1';
end case;
else
......@@ -214,7 +216,8 @@ begin
when c_WOA_BASE => rd(v_adr);
when c_ROA_BASE => rd(v_adr);
when c_EB_OPT => rd(v_adr);
when others => r_err <= '1';
when others => report "read to adr in cmd space not mapped";
r_err <= '1';
end case;
end if;
--STAGING AREA
......@@ -228,12 +231,9 @@ begin
--end if;
r_ack <= '1';
else
r_err <= '1'; -- a read on the framer ?! That's forbidden, give the user a scolding
end if;
--BAD/UNMAPPED ADR
r_err <= '1';
end if;
end if;
end if;
......
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