PUDC_B is connected to 1V8 instead of 1V8_AUX
PUDC_B is connected to wrong voltage rail.
This may create problem during board startup if 1V8 isn't powered before 1V8_AUX, because floating PUDC_B may activate pullups on all FPGA IO pins.
This could potentially explain our problems with half-populated DIOT crate, where 1V8 rail (powering IO banks) goes into OCP right after power-on.