verify power polygons
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Layer 4: Effective width copper on P3V3 polygon at area X: 143.6mm Y:59.8mm-62.8mm is 1.5mm. Is current and voltage enough for pins AJ28 and AF29? -
Layer 10: Effective width copper on VCC_PSPLL polygon around area X: 73.675mm Y:15.45 is 1.1mm. The voltage drop created by this bottleneck in conjunction with track of 0,6mm on bottom layer might be over the limits. -
Layer 14: Effective width copper on P1V8_AUX polygon is reduced to ~0.9mm
Check if those have enough current capacity. If not, duplicate the same polygons on other layers.