[L1] irregular (random?) traces thickness from FPGA pads
some FPGA (IC18) pads have thicker traces (0.24mm instead of 0.1mm) which makes sense for GND or power pins that connect to GND/power planes. However, sometimes it is also done for signal pins (e.g. M_SDA, M_SCL, P_IO0..2, etc.) but they immediately go to a via followed by normal 0.1mm width. Is this intentional?