[General] minor impedance discontinuities - on slow LVDS improve only if possible
- L5/L4PWR: minor impedance discontinuities (split in power plane crossings) - SLOT3_LVDS_0 and signals around (near FPGA pin A14)
- Idem for L3/L4PWR. Since the stackup is symmetric here, both power and ground planes affect the high speed signals in roughly same way. Example: SLOT2_LVDS_3 near FPGA pin C14.
- Idem for L12/L10/L11PWR.