Closed
Milestone
sch v1.0
Unstarted Issues (open and unassigned)
1
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
62
- CPCIS_Connectors_P1_P4_P6: Fix JTAG lines assignment to BP_DUAL diff pairs
- FPGA_Bank_44_64_65: LED_USER0 could be moved to Bank44
- Optimise bill-of-materials
- Connect SERVMOD also to FPGA pin
- FPGA_Bank_44_64_65: BP_IO.LVDS_P/N_12 isn't connected to FPGA diff pair
- USB_Quad and Power_Supply_3 could use the same LDO to produce 3V3 from 5V
- Re-annotate the whole schematics
- Add a startup oscillator that could be easily used before/instead programming Si5341
- Sensors: why they are powered from P3V3_reg and not from P3V3?
- FPGA_BANK_66_67_68_DDR: random indentation of net labels?
- FPGA_Bank_44_64_65: rename UART signals
- FPGA_Bank_44_64_65: SD_DETECT missing pull-up
- FPGA_Bank_0_CFG: "Connect RST_N to PROGRAM_B?" note
- DDR_SODIMM: orientation of pull-up and pull-down banks
- DDR4_SODIMM: VDDSPD should be P2V5
- BP_IO.GA0..3 shall be pulled-up on this board
- CPCIS_Connectors_P1_P4_P6: BP_DUAL and BP_IO LVDS diff pairs numbering shall reflect the cross-over in the backplane
- CPCIS_Connectors_P1_P4_P6: remove no-ERC directives from P4 connector row 6
- CPCIS_Connectors_P1_P4_P6: connect RST_N to RTM P4 pin E4
- CPCIS_Connectors_P1_P4_P6: provide power to RTM
- CPCIS_Connectors_P1_P4_P6: remove DECT_RIO and DECT_BPR as these signals are not used
- CPCIS_Connectors_P1_P4_P6: voltage levels incompatibility at IC5/6/7
- CPCIS_Connectors_P1_P4_P6:IC5/6/7 it would make sense to ground 2B2 and 4B2 through a pull-down resistor
- C156 is used above its voltage rating, C153 exactly on it
- CPCIS_Connectors_P1_P4_P6: check backplane signals naming with ZU7 System Board and make it consistent
- CPCIS_Connectors_P1_P4_P6: remove P5V0_MP
- rename SERVMOD_N to SERVMOD
- Survey OVERTHERM signal
- Don't put IC designators in comments
- explain BP acronym
- Note with a question may be removed? (page 10)
- R90 and R91 both 0 Ohm short power supplies. One should be "not mounted" (page 9)
- Page 6: why still wires connected to pins that are not used? Not on all either.
- R95 with R97 of 0 Ohm short P3V3 (page 5)
- Why T8 has no pull-down on EN_RTM_SHARED_BUS? T2-T7 have one. (page 5)
- Add a post-it type note on page 2 that Vadj is fixed 1.8V
- CERN OHL Licence should be -W instead of -S
- EN_USB_JTAG is always high when board is on power.
- JTAG functionality
- Excesive pull up on FMC-PS_N line
- JTAG lines pull resistors
- Error on SN74CB3T3257PW component design
- ESD strips and nets are floating.
- BSH103 is NRND
- Merging of passive parts : 3 types of 10uF caps
- Merging of passive parts : 2 types of 22uF caps
- Merging of passive parts : 2 types of 47uF caps
- P connectors index/legend should also include what is decided to be used within DIOT functionality
- Is a Power-up sequence diagram needed?
- Jtag Chain needs a block diagram for visualization
- Use one sheet symbol and schematic for each connector will relax connectors schematic
- Colouring of harness, wires, comments should take into account accessibility for color vision deficiency
- Explanatory heading is missing from some design schematic pages.
- Harness representation in schematics
- Remove Netlist Options so Only netnames define the netlist.
- FPGA JTAG pull-ups
- Question: power consumption/max. junction temp. power supplies (p. 11/12/13)
- Power dissipation Kintex UltraScale
- External DIO
- no-erc symbol for specific violation
- FPGA bank 44 64 65 sheet
- JTAG TCK/TMS sharing