DDR3 Controller for Xilinx Spartan6
Overview
This core is a DDR3 controller with two pipelined Wishbone slave
ports.
It is based on the Spartan6 hardware core and a management core
generated by Xilinx
CoreGen.
Documentation
The Spartan-6 FPGA Memory Controller is documented in the relevant Xilinx user guides:
- ug388 - Spartan-6 FPGA Memory Controller User Guide
- ug416 - Spartan-6 FPGA Memory Interface Solutions User Guide
Remember to also check the Xilinx support website for the latest versions of these documents.
Contacts
Maintainers
- Dimitris Lampridis - CERN
Status
Date | Event |
---|---|
16-08-2010 | Xilinx memory controller study |
18-08-2010 | Write a wrapper around core generated by Xilinx and add 2 wishbone slaves |
20-08-2010 | Test the core on SP605 dev kit, along with the FMC-ADC-100M-14b-4cha |
11-11-2010 | Publication of the prototype made for SP605 dev kit |
17-02-2016 | Project has new maintainer |