Commits · master · Projects / DDR3 controller for Spartan6

03 Nov, 2022 2 commits
- Merge branch 'release-v201' into 'master' · 01a07e1d
  Tristan Gingold authored Nov 03, 2022
```
Add an entry for v2.0.1

See merge request be-cem-edl/common/ddr3-sp6-core!1
```
  01a07e1d
- Add an entry for v2.0.1 · f692bc83
  Tristan Gingold authored Nov 03, 2022
  
  f692bc83
20 Oct, 2021 1 commit
- svec/ip_cores: create common/Manifest.py to gather common files · 2b8c861b
  Tristan Gingold authored Oct 20, 2021
```
Avoid multiple definition of the same unit.
Avoid warnings from hdlmake.
```
  2b8c861b
24 Jul, 2020 5 commits

Merge tag 'v2.0.0' into proposed_master · b84d0335

Dimitris Lampridis authored Jul 24, 2020

2.0.0 - 2020-07-24
=================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v2.0.0

Added
-----
- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench

Changed
-------
- Complete rewrite of the Wishbone interface to improve compatibility, performance and code readability

Removed
-------
- Unused file ``rtl/ddr3_ctrl_wb_single.vhd``

b84d0335

Merge branch 'release/2.0.0' · 70f9de31
Dimitris Lampridis authored Jul 24, 2020

70f9de31
bld: update changelog · e56167a1
Dimitris Lampridis authored Jul 24, 2020
```
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
e56167a1
bld: add CC0 licence · 1c41e228
Dimitris Lampridis authored Jul 24, 2020
```
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
1c41e228

[hdl] Complete rewrite of the Wishbone interface · 0bebda31

Dimitris Lampridis authored Jan 10, 2020

This is done in order to:

1. Fix incompatibilities with pipelined wishbone
2. Improve performance
3, Improve code readability

0bebda31

10 Jan, 2020 1 commit
- Introduce basic SV testbench · fa316ca7
  Dimitris Lampridis authored Dec 20, 2019
  
  fa316ca7
20 Dec, 2019 1 commit
- [doc] add bigger block diagram image · 39d4b2d0
  Dimitris Lampridis authored Dec 20, 2019
  
  39d4b2d0
25 Jul, 2019 6 commits
- Add granularity generic for both ports. · 1a129390
  Tristan Gingold authored Jul 25, 2019
  
  1a129390
- ddr3_ctrl_wb: save the last valid value of we. · 73878a95
  Tristan Gingold authored Jul 25, 2019
  
  73878a95
- ddr3_ctrl_wb: improve style. · adaeb417
  Tristan Gingold authored Jul 25, 2019
  
  adaeb417
- ddr3_ctrl_wb: remove unused signal. · edfed0ea
  Tristan Gingold authored Jul 25, 2019
  
  edfed0ea
- ddr3_ctrl_wb: add/remove comments. · 81eb9449
  Tristan Gingold authored Jul 25, 2019
  
  81eb9449
- ddr3_ctrl_wb: remove unused signals. · d78b2b5c
  Tristan Gingold authored Jul 25, 2019
  
  d78b2b5c
13 Dec, 2018 2 commits
- sim: auto-include ddr3 model when simulating · bb5b8f75
  Dimitris Lampridis authored Dec 13, 2018
  
  bb5b8f75
- ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the… · 405ce250
  Dimitris Lampridis authored Dec 13, 2018
```
ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the latter includes the former.
```
  405ce250
23 Nov, 2018 2 commits
- hdl: minor code cleanup · 33b31655
  Dimitris Lampridis authored Nov 23, 2018
  
  33b31655
- hdl: introduce option for active high reset to simplify reset logic · f2c4142a
  Dimitris Lampridis authored Nov 23, 2018
  
  f2c4142a
26 Oct, 2018 1 commit
- hdl: Migrate BFM for Micron DDR3 from FMC-ADC gateware project to here · 94a664ed
  Dimitris Lampridis authored Oct 26, 2018
  
  94a664ed
19 May, 2016 2 commits
- update headers in vhdl files and minor indentation fixes · 50317193
  Dimitris Lampridis authored May 19, 2016
  
  50317193
- hdl: add separate reset lines for WB interfaces, review reset logic, solves #214 · bd06069f
  Dimitris Lampridis authored May 19, 2016
  
  bd06069f
24 Feb, 2016 2 commits

hdl: fixed typo (wrong tabulation) · e4d6755c
Dimitris Lampridis authored Feb 24, 2016

e4d6755c

hdlmake: update top-level Manifest.py to not include any local variables · 16e35730

Dimitris Lampridis authored Feb 24, 2016

hdlmake does not allow by default local variables in included Manifest.py files. So, when this core is included in a bigger project (such as FMC-ADC), it should not have any local variables in its local Manifest.py file. Tested with SPEC and SVEC versions of FMC-ADC, works.

16e35730

25 Jun, 2015 1 commit
- Fix minor issues in top Manifest.py · 09f14bcf
  Javier D. Garcia-Lasheras authored Jun 25, 2015
  
  09f14bcf
17 Feb, 2015 1 commit
- hdlmake: Use conditionnal inclusion with custom variable (available in hdlmake v2.1). · f90e3701
  Matthieu Cattin authored Feb 17, 2015
  
  f90e3701
19 Jul, 2013 1 commit
- hdl: Fix wishbone interface. Now ignores stb if cyc is '0'. · 8de0e83e
  Matthieu Cattin authored Jul 19, 2013
  
  8de0e83e
28 Mar, 2013 1 commit
- hdl: Fix bug in wishbone interface. · 7f76b945
  Matthieu Cattin authored Mar 28, 2013
```
Command strobe should asserted even if it is already 1.
```
  7f76b945
30 Nov, 2012 1 commit

Fix bug in wishbone interface. · 26d0d907

Matthieu Cattin authored Nov 30, 2012

Was not porperly generating the command strobe to ddr interface in case
of wishbone block transfers.

26d0d907

19 Nov, 2012 1 commit
- Add a Manifest file to repo root directory. · 46df8a79
  Matthieu Cattin authored Nov 19, 2012
  
  46df8a79
16 Nov, 2012 2 commits
- Bug fix in command enable signal generation. · cd3680a0
  Matthieu Cattin authored Nov 16, 2012
```
The command enable signal was not properly generated for single read cycle.
```
  cd3680a0
- Remove common files and modify Manifests to take local files. · 5bd12eae
  Matthieu Cattin authored Nov 16, 2012
  
  5bd12eae
24 Oct, 2012 2 commits
- Bypass IBUFG in generated cores to avoid translation errors. · 00cdfb46
  mcattin authored Oct 24, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@110 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  00cdfb46
- Change RZQ pin for SVEC bank5 DDR controller from L25 (V0) to G25 (V1 or higher). · 0ac0a66d
  mcattin authored Oct 24, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@109 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  0ac0a66d
09 Aug, 2012 1 commit
- Modify bank port type selection default value in the component declaration. · e442e51a
  mcattin authored Aug 09, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@108 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  e442e51a
08 Aug, 2012 1 commit

Move common entities to a dedicated folder. · b8307a81

mcattin authored Aug 08, 2012

Modify Manifests accordingly.



git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@107 739e5516-d4a2-47df-ba96-5610c1fa693f

b8307a81

16 Jul, 2012 1 commit
- Bypass IBUFG in generated cores to avoid translation errors. · 59af43bc
  mcattin authored Jul 16, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@106 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  59af43bc
11 Jul, 2012 2 commits

Add missing vfc core components in wrapper package. · f28c1900
mcattin authored Jul 11, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@105 739e5516-d4a2-47df-ba96-5610c1fa693f
```
f28c1900

Remove generated cores with old naming. · c7c0e49e

mcattin authored Jul 11, 2012


git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@104 739e5516-d4a2-47df-ba96-5610c1fa693f

c7c0e49e