Commits · f2c4142ab8979a5857efc3f6921acf116f53eca4 · Projects / DDR3 controller for Spartan6

23 Nov, 2018 1 commit
- hdl: introduce option for active high reset to simplify reset logic · f2c4142a
  Dimitris Lampridis authored Nov 23, 2018
  
  f2c4142a
26 Oct, 2018 1 commit
- hdl: Migrate BFM for Micron DDR3 from FMC-ADC gateware project to here · 94a664ed
  Dimitris Lampridis authored Oct 26, 2018
  
  94a664ed
19 May, 2016 2 commits
- update headers in vhdl files and minor indentation fixes · 50317193
  Dimitris Lampridis authored May 19, 2016
  
  50317193
- hdl: add separate reset lines for WB interfaces, review reset logic, solves #214 · bd06069f
  Dimitris Lampridis authored May 19, 2016
  
  bd06069f
24 Feb, 2016 2 commits

hdl: fixed typo (wrong tabulation) · e4d6755c
Dimitris Lampridis authored Feb 24, 2016

e4d6755c

hdlmake: update top-level Manifest.py to not include any local variables · 16e35730

Dimitris Lampridis authored Feb 24, 2016

hdlmake does not allow by default local variables in included Manifest.py files. So, when this core is included in a bigger project (such as FMC-ADC), it should not have any local variables in its local Manifest.py file. Tested with SPEC and SVEC versions of FMC-ADC, works.

16e35730

25 Jun, 2015 1 commit
- Fix minor issues in top Manifest.py · 09f14bcf
  Javier D. Garcia-Lasheras authored Jun 25, 2015
  
  09f14bcf
17 Feb, 2015 1 commit
- hdlmake: Use conditionnal inclusion with custom variable (available in hdlmake v2.1). · f90e3701
  Matthieu Cattin authored Feb 17, 2015
  
  f90e3701
19 Jul, 2013 1 commit
- hdl: Fix wishbone interface. Now ignores stb if cyc is '0'. · 8de0e83e
  Matthieu Cattin authored Jul 19, 2013
  
  8de0e83e
28 Mar, 2013 1 commit
- hdl: Fix bug in wishbone interface. · 7f76b945
  Matthieu Cattin authored Mar 28, 2013
```
Command strobe should asserted even if it is already 1.
```
  7f76b945
30 Nov, 2012 1 commit

Fix bug in wishbone interface. · 26d0d907

Matthieu Cattin authored Nov 30, 2012

Was not porperly generating the command strobe to ddr interface in case
of wishbone block transfers.

26d0d907

19 Nov, 2012 1 commit
- Add a Manifest file to repo root directory. · 46df8a79
  Matthieu Cattin authored Nov 19, 2012
  
  46df8a79
16 Nov, 2012 2 commits
- Bug fix in command enable signal generation. · cd3680a0
  Matthieu Cattin authored Nov 16, 2012
```
The command enable signal was not properly generated for single read cycle.
```
  cd3680a0
- Remove common files and modify Manifests to take local files. · 5bd12eae
  Matthieu Cattin authored Nov 16, 2012
  
  5bd12eae
24 Oct, 2012 2 commits
- Bypass IBUFG in generated cores to avoid translation errors. · 00cdfb46
  mcattin authored Oct 24, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@110 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  00cdfb46
- Change RZQ pin for SVEC bank5 DDR controller from L25 (V0) to G25 (V1 or higher). · 0ac0a66d
  mcattin authored Oct 24, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@109 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  0ac0a66d
09 Aug, 2012 1 commit
- Modify bank port type selection default value in the component declaration. · e442e51a
  mcattin authored Aug 09, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@108 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  e442e51a
08 Aug, 2012 1 commit

Move common entities to a dedicated folder. · b8307a81

mcattin authored Aug 08, 2012

Modify Manifests accordingly.



git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@107 739e5516-d4a2-47df-ba96-5610c1fa693f

b8307a81

16 Jul, 2012 1 commit
- Bypass IBUFG in generated cores to avoid translation errors. · 59af43bc
  mcattin authored Jul 16, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@106 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  59af43bc
11 Jul, 2012 6 commits

Add missing vfc core components in wrapper package. · f28c1900
mcattin authored Jul 11, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@105 739e5516-d4a2-47df-ba96-5610c1fa693f
```
f28c1900

Remove generated cores with old naming. · c7c0e49e

mcattin authored Jul 11, 2012


git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@104 739e5516-d4a2-47df-ba96-5610c1fa693f

c7c0e49e

Modify generated core naming to include board reference. · 137e2d48

mcattin authored Jul 11, 2012

This is to allow different configuration (FPGA/memory chip) for the same port.
Add re-generated core with new names.

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@103 739e5516-d4a2-47df-ba96-5610c1fa693f

137e2d48

Cleanup VFC ip_cores directory. · ce769f0f

mcattin authored Jul 11, 2012


git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@102 739e5516-d4a2-47df-ba96-5610c1fa693f

ce769f0f

More cleanup. · d973d96f

mcattin authored Jul 11, 2012


git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@101 739e5516-d4a2-47df-ba96-5610c1fa693f

d973d96f

Cleanup unused files and directories. · 24f989dc

mcattin authored Jul 11, 2012


git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@100 739e5516-d4a2-47df-ba96-5610c1fa693f

24f989dc

10 Jul, 2012 1 commit

Remove IBUFG from core. Was causing error during translation, because the buffer… · 5d69a3a4

mcattin authored Jul 10, 2012

Remove IBUFG from core. Was causing error during translation, because the buffer wasn't connected to a top port. (see AR #22252).

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@99 739e5516-d4a2-47df-ba96-5610c1fa693f

5d69a3a4

09 Jul, 2012 5 commits
- Fix port name mismatch after core upgrade. · d1ab2bbb
  mcattin authored Jul 09, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@98 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  d1ab2bbb
- Add missing ddr3_ctrl_wrapper_pkg to Manifest file. · 17dc26bb
  mcattin authored Jul 09, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@97 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  17dc26bb
- Add Manifest files in generated cores directories. · 12cfb76f
  mcattin authored Jul 09, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@96 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  12cfb76f
- Cleanup. Remove unused directories. · d7839242
  mcattin authored Jul 09, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@95 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  d7839242
- Add support for 64b_32b. Regenerate all spec and svec cores. · 2eed5034
  mcattin authored Jul 09, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@94 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  2eed5034
06 Jul, 2012 1 commit
- Add missing status port assignment on core top level · dbb956f6
  mcattin authored Jul 06, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@93 739e5516-d4a2-47df-ba96-5610c1fa693f
```
  dbb956f6
05 Jul, 2012 2 commits

Add FIFO status ports to the ddr core top level. · 829319ac
mcattin authored Jul 05, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@92 739e5516-d4a2-47df-ba96-5610c1fa693f
```
829319ac

Add wrapper and Manifest for SVEC. · 8bd9ddf4

mcattin authored Jul 05, 2012

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@91 739e5516-d4a2-47df-ba96-5610c1fa693f

8bd9ddf4

25 Jun, 2012 2 commits

Add ip_cores directory for ddr3 interface developement on SVEC. · c960fd92
mcattin authored Jun 25, 2012
```
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@90 739e5516-d4a2-47df-ba96-5610c1fa693f
```
c960fd92

Add SVEC directory. · d5db4dcf

mcattin authored Jun 25, 2012

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@89 739e5516-d4a2-47df-ba96-5610c1fa693f

d5db4dcf

06 Feb, 2012 2 commits

Add LGPL header. · 2434d86e

mcattin authored Feb 06, 2012

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@88 739e5516-d4a2-47df-ba96-5610c1fa693f

2434d86e

Add LGPL license to hdl top folder. · 5320d30e

mcattin authored Feb 06, 2012

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@87 739e5516-d4a2-47df-ba96-5610c1fa693f

5320d30e

09 Dec, 2011 2 commits

Fix bug, was wb_we = 1 instead of wb_we = 0. · cbaa6485

mcattin authored Dec 09, 2011

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@86 739e5516-d4a2-47df-ba96-5610c1fa693f

cbaa6485

Previous commit was data loss when writing to the DDR in burst smaller than… · 221d1e40

mcattin authored Dec 09, 2011

Previous commit was data loss when writing to the DDR in burst smaller than c_DDR_BURST_LENGTH. Use wb_stb falling edge only on read cycles, use wb_we falling edge for write cycles.

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@85 739e5516-d4a2-47df-ba96-5610c1fa693f

221d1e40