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DDR3 controller for Spartan6
Commit fa316ca7 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Introduce basic SV testbench

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CHANGELOG.md 0 → 100644
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# Changelog
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
## [Unreleased]
### Added
- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench
## [1.0.0] - 2016-05-19
### Added
- First release
[Unreleased]: https://www.ohwr.org/project/ddr3-sp6-core/compare/v1.0.0...proposed_master
[1.0.0]: https://www.ohwr.org/project/ddr3-sp6-core/tags/v1.0.0
hdl/testbench/.gitignore 0 → 100644
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work/
NullFile
Makefile
modelsim.ini
transcript*
*.wlf
wlf*
buildinfo_pkg.vhd
hdl/testbench/Manifest.py 0 → 100644
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board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
# Use fetchto to point to parent folder of general-cores, like this:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../"
include_dirs = [
fetchto + "/general-cores/sim",
]
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../",
fetchto + "/general-cores",
],
}
ctrls = ["bank3_32b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/main.sv 0 → 100644
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//------------------------------------------------------------------------------
// CERN BE-CO-HT
// DDR3 Controller for Xilinx Spartan6
// http://www.ohwr.org/projects/ddr3-sp6-core
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: Testbench for the Xilinx Spartan-6 DDR3 Controller.
//
//------------------------------------------------------------------------------
// Copyright CERN 2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ns/1ps
`include "if_wb_master.svh"
module main;
reg clk_333m = 0;
reg clk_125m = 0;
always #1.5ns clk_333m <= ~clk_333m;
always #4.0ns clk_125m <= ~clk_125m;
wire ddr_cas_n, ddr_ck_p, ddr_ck_n, ddr_cke;
wire [1:0] ddr_dm, ddr_dqs_p, ddr_dqs_n;
wire ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n;
wire [15:0] ddr_dq;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_rzq;
logic rst_n;
IWishboneMaster I_wb (clk_125m, rst_n);
//---------------------------------------------------------------------------
// The DUT
//---------------------------------------------------------------------------
ddr3_ctrl #
(
.g_RST_ACT_LOW (1),
.g_SIMULATION ("TRUE"),
.g_CALIB_SOFT_IP ("FALSE")
)
DUT
(
.clk_i (clk_333m),
.rst_n_i (rst_n),
.ddr3_dq_b (ddr_dq),
.ddr3_a_o (ddr_a),
.ddr3_ba_o (ddr_ba),
.ddr3_ras_n_o (ddr_ras_n),
.ddr3_cas_n_o (ddr_cas_n),
.ddr3_we_n_o (ddr_we_n),
.ddr3_odt_o (ddr_odt),
.ddr3_rst_n_o (ddr_reset_n),
.ddr3_cke_o (ddr_cke),
.ddr3_dm_o (ddr_dm[0]),
.ddr3_udm_o (ddr_dm[1]),
.ddr3_dqs_p_b (ddr_dqs_p[0]),
.ddr3_dqs_n_b (ddr_dqs_n[0]),
.ddr3_udqs_p_b (ddr_dqs_p[1]),
.ddr3_udqs_n_b (ddr_dqs_n[1]),
.ddr3_clk_p_o (ddr_ck_p),
.ddr3_clk_n_o (ddr_ck_n),
.ddr3_rzq_b (ddr_rzq),
.wb0_rst_n_i (rst_n),
.wb0_clk_i (clk_125m),
.wb0_sel_i (I_wb.sel),
.wb0_cyc_i (I_wb.cyc),
.wb0_stb_i (I_wb.stb),
.wb0_we_i (I_wb.we),
.wb0_addr_i (I_wb.adr),
.wb0_data_i (I_wb.dat_o),
.wb0_data_o (I_wb.dat_i),
.wb0_ack_o (I_wb.ack),
.wb0_stall_o (I_wb.stall)
);
//---------------------------------------------------------------------------
// DDR memory model
//---------------------------------------------------------------------------
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
DDR_MEM
(
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs (ddr_dm),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs (ddr_dqs_p),
.dqs_n (ddr_dqs_n),
.tdqs_n (),
.odt (ddr_odt)
);
CWishboneAccessor acc;
wb_cycle_t c,r;
wb_xfer_t x;
const int c_NPACKETS = 200000;
const int c_ADDR_BASE = 0;
const int c_DATA_BASE = 0;
initial begin
int i;
time wr_t, rd_t;
$timeformat (-6, 3, "us", 10);
$display();
$display("-------------------");
$display("Start of simulation");
$display("-------------------");
$display();
rst_n = 1'b0;
#1us;
rst_n = 1'b1;
acc = I_wb.get_accessor();
// Prime the DDR by writing a couple of dummy bursts
c.ctype = PIPELINED;
c.rw = 1;
c.data.delete();
for (i = 0; i < 100; i++) begin
x.a = c_ADDR_BASE + 4*i;
x.d = c_DATA_BASE + i;
x.size = 4;
c.data.push_back(x);
end
acc.put(c);
acc.get(r);
#10us;
// Perform write test
$display("- Begin write test (%0d bytes)", c_NPACKETS * 4);
c.ctype = PIPELINED;
c.rw = 1;
c.data.delete();
for (i = 0; i < c_NPACKETS; i++) begin
x.a = c_ADDR_BASE + 4*i;
x.d = c_DATA_BASE + i;
x.size = 4;
c.data.push_back(x);
end
wr_t = $time;
acc.put(c);
acc.get(r);
wr_t = $time - wr_t;
$display(" %0d bytes written to DDR in %0t (%0.2f MB/s)",
c_NPACKETS * 4, wr_t, 1e3 * c_NPACKETS * 4.0 / wr_t);
#10us;
// Perform read test
$display("- Begin read test (%0d bytes)", c_NPACKETS * 4);
c.ctype = PIPELINED;
c.rw = 0;
c.data.delete();
for (i = 0; i < c_NPACKETS; i++) begin
x.a = c_ADDR_BASE + 4*i;
x.size = 4;
c.data.push_back(x);
end
rd_t = $time;
acc.put(c);
acc.get(r);
rd_t = $time - rd_t;
$display(" %0d bytes read back from DDR in %0t (%0.2f MB/s)",
c_NPACKETS * 4, rd_t, 1e3 * c_NPACKETS * 4.0 / rd_t);
$display("- Data verification");
for (i = 0; i < c_NPACKETS; i++) begin
if (r.data[i].d != c_DATA_BASE + i)
$error("Read-back error at address %8x. Expected %8x, but got %8x instead",
r.data[i].a, c_DATA_BASE + i, r.data[i].d);
end
$display(" done");
#1us;
$display();
$display("-------------------");
$display("Simulation PASSED");
$display("-------------------");
$display();
$finish;
end
endmodule // main
hdl/testbench/run.do 0 → 100644
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vsim -voptargs=+acc=lprn -quiet -t 10fs -L unisim -L secureip work.main -suppress 8822,8617,8683,8684
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
hdl/testbench/run_ci.do 0 → 100644
View file @ fa316ca7
vsim -voptargs=+acc=lprn -quiet -t 10fs -L unisim -L secureip work.main -suppress 8822,8617,8683,8684
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
run -all
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