Commit e56167a1 authored by Dimitris Lampridis's avatar Dimitris Lampridis

bld: update changelog

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 1c41e228
# Changelog
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
## [Unreleased]
### Added
- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench
### Changed
- Complete rewrite of the Wishbone interface to improve performance and code readability
### Removed
- Unused file `rtl/ddr3_ctrl_wb_single.vhd`
## [1.0.0] - 2016-05-19
### Added
- First release
[Unreleased]: https://www.ohwr.org/project/ddr3-sp6-core/compare/v1.0.0...proposed_master
[1.0.0]: https://www.ohwr.org/project/ddr3-sp6-core/tags/v1.0.0
..
SPDX-License-Identifier: CC0-1.0
SPDX-FileCopyrightText: 2019-2020 CERN
==========
Change Log
==========
- Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
- Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
2.0.0 - 2020-07-24
=================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v2.0.0
Added
-----
- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench
Changed
-------
- Complete rewrite of the Wishbone interface to improve compatibility, performance and code readability
Removed
-------
- Unused file ``rtl/ddr3_ctrl_wb_single.vhd``
1.0.0 - 2016-05-19
==================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v1.0.0
Added
-----
- First release
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