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DDR3 controller for Spartan6
Commit 8de0e83e authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Fix wishbone interface. Now ignores stb if cyc is '0'.

parent 7f76b945
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Showing with 9 additions and 5 deletions
hdl/rtl/ddr3_ctrl_wb.vhd
View file @ 8de0e83e
......@@ -143,6 +143,7 @@ architecture rtl of ddr3_ctrl_wb is
signal wb_cyc_d : std_logic;
signal wb_cyc_f_edge : std_logic;
signal wb_cyc_r_edge : std_logic;
signal wb_stb_valid : std_logic;
signal wb_stb_d : std_logic;
signal wb_stb_f_edge : std_logic;
signal wb_we_d : std_logic;
......@@ -188,6 +189,9 @@ begin
ddr_wr_clk_o <= wb_clk_i;
ddr_rd_clk_o <= wb_clk_i;
-- stb is valid only if cyc is '1'
wb_stb_valid <= wb_stb_i and wb_cyc_i;
-- Cycle, we and strobe rising and falling edge detection
p_wb_cyc_f_edge : process (wb_clk_i)
begin
......@@ -198,7 +202,7 @@ begin
wb_we_d <= '0';
else
wb_cyc_d <= wb_cyc_i;
wb_stb_d <= wb_stb_i;
wb_stb_d <= wb_stb_valid;
wb_we_d <= wb_we_i;
end if;
end if;
......@@ -206,7 +210,7 @@ begin
wb_cyc_f_edge <= not(wb_cyc_i) and wb_cyc_d;
wb_cyc_r_edge <= wb_cyc_i and not(wb_cyc_d);
wb_stb_f_edge <= not(wb_stb_i) and wb_stb_d;
wb_stb_f_edge <= not(wb_stb_valid) and wb_stb_d;
wb_we_f_edge <= not(wb_we_i) and wb_we_d;
-- Data inputs
......@@ -217,7 +221,7 @@ begin
ddr_wr_data <= (others => '0');
ddr_wr_en <= '0';
else
if (wb_stb_i = '1') and (wb_cyc_i = '1') and (wb_we_i = '1') then
if (wb_stb_valid = '1') and (wb_cyc_i = '1') and (wb_we_i = '1') then
ddr_wr_en <= '1';
else
ddr_wr_en <= '0';
......@@ -239,7 +243,7 @@ begin
wb_addr_d <= (others => '0');
else
wb_addr_d <= wb_addr_i;
if ((ddr_burst_cnt = 0 and wb_cyc_r_edge = '1' and wb_stb_i = '1') or
if ((ddr_burst_cnt = 0 and wb_cyc_r_edge = '1' and wb_stb_valid = '1') or
(ddr_burst_cnt = to_unsigned(1, ddr_burst_cnt'length))) then
ddr_cmd_byte_addr <= wb_addr_d(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift;
ddr_cmd_instr <= "00" & not(wb_we_d);
......@@ -283,7 +287,7 @@ begin
else
if (wb_cyc_f_edge = '1') then
ddr_burst_cnt <= to_unsigned(0, ddr_burst_cnt'length);
elsif (wb_stb_i = '1' and wb_cyc_i = '1') then
elsif (wb_stb_valid = '1' and wb_cyc_i = '1') then
if (ddr_burst_cnt = c_DDR_BURST_LENGTH) then
ddr_burst_cnt <= to_unsigned(1, ddr_burst_cnt'length);
else
......
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