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DDR3 controller for Spartan6
Commit 70f9de31 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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SPDX-License-Identifier: CC0-1.0
SPDX-FileCopyrightText: 2019-2020 CERN
==========
Change Log
==========
- Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
- Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
2.0.0 - 2020-07-24
=================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v2.0.0
Added
-----
- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench
Changed
-------
- Complete rewrite of the Wishbone interface to improve compatibility, performance and code readability
Removed
-------
- Unused file ``rtl/ddr3_ctrl_wb_single.vhd``
1.0.0 - 2016-05-19
==================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v1.0.0
Added
-----
- First release
LICENCES/CC0-1.0.txt 0 → 100644
View file @ 70f9de31
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hdl/rtl/ddr3_ctrl.vhd
View file @ 70f9de31
......@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-07-13
-- Last update: 2018-11-12
-- Last update: 2020-07-07
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Wishbone to DDR3 interface for Xilinx FPGA with MCB (Memory
......@@ -59,6 +59,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
use work.wishbone_pkg.all;
--==============================================================================
--! Entity declaration for ddr3_ctrl
......@@ -90,12 +91,16 @@ entity ddr3_ctrl is
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Port 0 address granularity
g_P0_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
g_P1_BYTE_ADDR_WIDTH : integer := 30;
--! Port 0 address granularity
g_P1_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD
);
port(
......@@ -333,9 +338,10 @@ begin
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wb_0 : entity work.ddr3_ctrl_wb
generic map(
g_BYTE_ADDR_WIDTH => g_P0_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P0_MASK_SIZE,
g_DATA_PORT_SIZE => g_P0_DATA_PORT_SIZE
g_BYTE_ADDR_WIDTH => g_P0_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P0_MASK_SIZE,
g_DATA_PORT_SIZE => g_P0_DATA_PORT_SIZE,
g_ADDR_GRANULARITY => g_P0_ADDR_GRANULARITY
)
port map(
rst_n_i => wb0_rst_n_i,
......@@ -363,6 +369,7 @@ begin
ddr_rd_count_i => p0_rd_count,
ddr_rd_overflow_i => p0_rd_overflow,
ddr_rd_error_i => p0_rd_error,
wb_rst_n_i => wb0_rst_n_i,
wb_clk_i => wb0_clk_i,
wb_sel_i => wb0_sel_i,
wb_cyc_i => wb0_cyc_i,
......@@ -380,9 +387,10 @@ begin
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wb_1 : entity work.ddr3_ctrl_wb
generic map(
g_BYTE_ADDR_WIDTH => g_P1_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P1_MASK_SIZE,
g_DATA_PORT_SIZE => g_P1_DATA_PORT_SIZE
g_BYTE_ADDR_WIDTH => g_P1_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P1_MASK_SIZE,
g_DATA_PORT_SIZE => g_P1_DATA_PORT_SIZE,
g_ADDR_GRANULARITY => g_P1_ADDR_GRANULARITY
)
port map(
rst_n_i => wb1_rst_n_i,
......@@ -410,6 +418,7 @@ begin
ddr_rd_count_i => p1_rd_count,
ddr_rd_overflow_i => p1_rd_overflow,
ddr_rd_error_i => p1_rd_error,
wb_rst_n_i => wb1_rst_n_i,
wb_clk_i => wb1_clk_i,
wb_sel_i => wb1_sel_i,
wb_cyc_i => wb1_cyc_i,
......
hdl/rtl/ddr3_ctrl_wb.vhd
View file @ 70f9de31
-------------------------------------------------------------------------------
-- Title : DDR3 Controller Wishbone Interface
-- Project : DDR3 Controller for Xilinx Spartan6
-- URL : http://www.ohwr.org/projects/ddr3-sp6-core
-------------------------------------------------------------------------------
-- File : ddr3_ctrl.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-07-13
-- Last update: 2018-12-13
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Wishbone interface for DDR3 controller.
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-05-19 1.0 Dimitrios Lampridis
-- 2011-07-12 0.1 Matthieu Cattin
-------------------------------------------------------------------------------
--==============================================================================
-- doxygen info
--
--! @file ddr3_ctrl_wb.vhd
--! @brief DDR3 Controller Wishbone Interface
--! @details
--! Wishbone interface for DDR3 controller.
--! @version 2016-05-19 | 1.0 | Dimitrios Lampridis
--! @version 2011-07-12 | 0.1 | Matthieu Cattin
--! @author Matthieu Cattin, CERN (BE-CO-HT)
--! @author Dimitrios Lampridis, CERN (BE-CO-HT)
--
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- DDR3 Controller for Xilinx Spartan6
-- http://www.ohwr.org/projects/ddr3-sp6-core
--------------------------------------------------------------------------------
--
-- unit name: ddr3_ctrl_wb
--
-- description: Wishbone interface for DDR3 controller.
--
-- Important restrictions:
-- * pipelined wishbone only
-- * cannot mix read and writes during the same wishbone cycle
-- * must use consecutive addresses during the same wishbone cycle
-- * must drop CYC when done
--
--------------------------------------------------------------------------------
-- Copyright CERN 2011-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
--==============================================================================
--! Entity declaration for ddr3_ctrl_wb
--==============================================================================
entity ddr3_ctrl_wb is
generic(
--! DDR3 byte address width
g_BYTE_ADDR_WIDTH : integer := 30;
--! Data mask size (8-bit granularity)
g_MASK_SIZE : integer := 4;
--! Data width
g_DATA_PORT_SIZE : integer := 32
-- DDR3 byte address width
g_BYTE_ADDR_WIDTH : integer := 30;
-- Data mask size (8-bit granularity)
g_MASK_SIZE : integer := 4;
-- Data width
g_DATA_PORT_SIZE : integer := 32;
-- Granularity for wb_addr_i signal (BYTE|WORD)
g_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD
);
port(
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
......@@ -108,259 +82,380 @@ entity ddr3_ctrl_wb is
ddr_rd_count_i : in std_logic_vector(6 downto 0);
ddr_rd_overflow_i : in std_logic;
ddr_rd_error_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic
);
wb_rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic);
end entity ddr3_ctrl_wb;
architecture arch of ddr3_ctrl_wb is
------------------------------------------------------------------------------
-- Constants and functions declaration
------------------------------------------------------------------------------
--==============================================================================
--! Architecure declaration for ddr3_ctrl_wb
--==============================================================================
architecture rtl of ddr3_ctrl_wb is
-- Since the Command FIFO of the DDR is 4-deep and its Read/Write FIFOs are
-- 64-deep, we set the burst length to 16, to allow four commands to span
-- the full data FIFO.
constant c_DDR_BURST_LEN : integer := 16;
-- How many more commands to store locally. Having a small local CMD FIFO
-- (along with a WR and RD FIFO) helps with reaching timing closure.
constant c_CMD_FIFO_DEPTH : integer := 2;
constant c_WR_FIFO_DEPTH : integer := c_CMD_FIFO_DEPTH * c_DDR_BURST_LEN;
constant c_RD_FIFO_DEPTH : integer := c_CMD_FIFO_DEPTH * c_DDR_BURST_LEN;
constant c_CMD_FIFO_WIDTH : integer := g_BYTE_ADDR_WIDTH + 9;
constant c_WR_FIFO_WIDTH : integer := g_DATA_PORT_SIZE + g_MASK_SIZE;
constant c_RD_FIFO_WIDTH : integer := g_DATA_PORT_SIZE;
-- all command addresses need to be aligned to g_DATA_PORT_SIZE as per UG388.
-- g_ADDR_GRANULARITY = WORD:
-- 32bit data: cmd_addr[29..2] <= wb_addr[27..0]
-- 64bit data: cmd_addr[29..3] <= wb_addr[27..1]
-- 128bit data: cmd_addr[29..4] <= wb_addr[27..2]
-- g_ADDR_GRANULARITY = BYTE:
-- 32bit data: cmd_addr[29..2] <= wb_addr[29..2]
-- 64bit data: cmd_addr[29..3] <= wb_addr[29..3]
-- 128bit data: cmd_addr[29..4] <= wb_addr[29..4]
function f_align_addr (constant addr : std_logic_vector) return std_logic_vector is
variable l2ds : integer;
variable ret : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
begin
l2ds := log2_ceil(g_DATA_PORT_SIZE/8);
ret := (others => '0');
if g_ADDR_GRANULARITY = WORD then
ret(g_BYTE_ADDR_WIDTH-1 downto l2ds) :=
addr(g_BYTE_ADDR_WIDTH-3 downto l2ds-2);
else
ret(g_BYTE_ADDR_WIDTH-1 downto l2ds) :=
addr(g_BYTE_ADDR_WIDTH-1 downto l2ds);
end if;
return ret;
end function f_align_addr;
------------------------------------------------------------------------------
-- Constants declaration
-- Signals and types declaration
------------------------------------------------------------------------------
constant c_DDR_BURST_LENGTH : integer := 32; -- must not exceed 63
constant c_FIFO_ALMOST_FULL : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(57, 7));
type t_cmd_fsm_state is (S_IDLE, S_BUILD_BURST, S_EXEC_BURST);
constant c_ADDR_SHIFT : integer := log2_ceil(g_DATA_PORT_SIZE/8);
signal cmd_fsm_state : t_cmd_fsm_state := S_IDLE;
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
--type t_wb_fsm_states is (WB_IDLE, WB_WRITE, WB_READ_REQ, WB_READ_WAIT,
-- WB_READ_ACK, WB_READ_REQ_ACK);
signal wb_stall : std_logic := '0';
signal wb_stb_valid : std_logic := '0';
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal ddr_wr_en : std_logic := '0';
signal ddr_cmd_en : std_logic := '0';
signal ddr_cmd_instr : std_logic_vector(2 downto 0) := (others => '0');
signal ddr_cmd_bl : std_logic_vector(5 downto 0) := (others => '0');
signal wb_cyc_d : std_logic;
signal wb_cyc_f_edge : std_logic;
signal wb_cyc_r_edge : std_logic;
signal wb_stb_valid : std_logic;
signal wb_stb_d : std_logic;
signal wb_stb_f_edge : std_logic;
signal wb_we_d : std_logic;
signal wb_we_f_edge : std_logic;
signal wb_addr_d : std_logic_vector(31 downto 0);
signal ddr_burst_cnt : unsigned(5 downto 0);
signal ddr_cmd_en : std_logic;
signal ddr_cmd_en_d : std_logic;
signal ddr_cmd_en_r_edge : std_logic;
signal ddr_cmd_instr : std_logic_vector(2 downto 0);
signal ddr_cmd_bl : std_logic_vector(5 downto 0);
signal ddr_cmd_byte_addr : std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
signal addr_shift : std_logic_vector(c_ADDR_SHIFT-1 downto 0);
signal ddr_wr_en : std_logic;
signal ddr_wr_mask : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal ddr_wr_data : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal ddr_rd_en : std_logic;
--==============================================================================
--! Architecure begin
--==============================================================================
begin
signal ddr_cmd_byte_addr : std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal cmd_fifo_din : std_logic_vector(c_CMD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal cmd_fifo_dout : std_logic_vector(c_CMD_FIFO_WIDTH-1 downto 0) := (others => '0');
------------------------------------------------------------------------------
-- Wishbone interface
------------------------------------------------------------------------------
signal cmd_fifo_we : std_logic := '0';
signal cmd_fifo_rd : std_logic := '0';
signal cmd_fifo_full : std_logic := '0';
signal cmd_fifo_empty : std_logic := '0';
-- Clocking
ddr_cmd_clk_o <= wb_clk_i;
ddr_wr_clk_o <= wb_clk_i;
ddr_rd_clk_o <= wb_clk_i;
signal cmd_fifo_rd_disable : std_logic := '0';
-- stb is valid only if cyc is '1'
wb_stb_valid <= wb_stb_i and wb_cyc_i;
signal ddr_cmd_en_out : std_logic := '0';
-- Cycle, we and strobe rising and falling edge detection
p_wb_cyc_f_edge : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (rst_n_i = '0') then
wb_cyc_d <= '0';
wb_stb_d <= '0';
wb_we_d <= '0';
else
wb_cyc_d <= wb_cyc_i;
wb_stb_d <= wb_stb_valid;
wb_we_d <= wb_we_i;
end if;
end if;
end process p_wb_cyc_f_edge;
signal wr_fifo_din : std_logic_vector(c_WR_FIFO_WIDTH-1 downto 0) := (others => '0');
signal wr_fifo_dout : std_logic_vector(c_WR_FIFO_WIDTH-1 downto 0) := (others => '0');
wb_cyc_f_edge <= not(wb_cyc_i) and wb_cyc_d;
wb_cyc_r_edge <= wb_cyc_i and not(wb_cyc_d);
wb_stb_f_edge <= not(wb_stb_valid) and wb_stb_d;
wb_we_f_edge <= not(wb_we_i) and wb_we_d;
signal wr_fifo_we : std_logic := '0';
signal wr_fifo_rd : std_logic := '0';
signal wr_fifo_full : std_logic := '0';
signal wr_fifo_empty : std_logic := '0';
-- Data inputs
p_ddr_inputs : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (rst_n_i = '0') then
ddr_wr_data <= (others => '0');
ddr_wr_en <= '0';
else
if (wb_stb_valid = '1') and (wb_we_i = '1') then
ddr_wr_en <= '1';
else
ddr_wr_en <= '0';
end if;
ddr_wr_data <= wb_data_i;
ddr_wr_mask <= not(wb_sel_i);
end if;
end if;
end process p_ddr_inputs;
signal rd_fifo_din : std_logic_vector(c_RD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal rd_fifo_dout : std_logic_vector(c_RD_FIFO_WIDTH-1 downto 0) := (others => '0');
-- Command parameters (burst length and address) registration
p_ddr_cmd : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (rst_n_i = '0') then
ddr_cmd_byte_addr <= (others => '0');
ddr_cmd_instr <= "000";
ddr_cmd_bl <= (others => '0');
wb_addr_d <= (others => '0');
else
wb_addr_d <= wb_addr_i;
if ((ddr_burst_cnt = 0 and wb_cyc_r_edge = '1' and wb_stb_valid = '1') or
(ddr_burst_cnt = to_unsigned(1, ddr_burst_cnt'length))) then
ddr_cmd_byte_addr <= wb_addr_d(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift;
ddr_cmd_instr <= "00" & not(wb_we_d);
end if;
ddr_cmd_bl <= std_logic_vector(ddr_burst_cnt - 1);
end if;
end if;
end process p_ddr_cmd;
signal rd_fifo_we : std_logic := '0';
signal rd_fifo_rd : std_logic := '0';
signal rd_fifo_full : std_logic := '0';
signal rd_fifo_empty : std_logic := '0';
addr_shift <= (others => '0');
begin
-- Command enable signal generation
p_ddr_cmd_en : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if (rst_n_i = '0') then
ddr_cmd_en <= '0';
ddr_cmd_en_d <= '0';
else
ddr_cmd_en_d <= ddr_cmd_en;
if (((ddr_burst_cnt = c_DDR_BURST_LENGTH) or
(wb_cyc_f_edge = '1' and wb_we_d = '1') or
(wb_stb_f_edge = '1' and wb_we_d = '0')) and ddr_cmd_full_i = '0') then
ddr_cmd_en <= '1'; -- might have problem if burst_cnt = BURST_LENGTH for more than 2 clk cycles
else
ddr_cmd_en <= '0';
end if;
end if;
end if;
end process p_ddr_cmd_en;
------------------------------------------------------------------------------
-- Sanity checks
------------------------------------------------------------------------------
-- Only port sizes of 32, 64, and 128 are supported, as per UG388.
assert (g_DATA_PORT_SIZE = 32 or g_DATA_PORT_SIZE = 64 or g_DATA_PORT_SIZE = 128)
report "Provided data port size must be 32, 64 or 128" severity FAILURE;
-- Command path assertions
assert unsigned(ddr_cmd_byte_addr(f_log2_ceil(g_DATA_PORT_SIZE/8)-1 downto 0)) = 0
report "CMD byte address to data port size misalignment" severity FAILURE;
-- Write datapath assertions
assert ddr_wr_underrun_i /= '1'
report "WR FIFO underrun" severity FAILURE;
assert ddr_wr_error_i /= '1'
report "WR FIFO error" severity FAILURE;
-- Read datapath assertions
assert ddr_rd_overflow_i /= '1'
report "RD FIFO overflow" severity FAILURE;
assert ddr_rd_error_i /= '1'
report "RD FIFO error" severity FAILURE;
-- Command enable rising edge detection
ddr_cmd_en_r_edge <= ddr_cmd_en and not(ddr_cmd_en_d);
------------------------------------------------------------------------------
-- CMD, WR and RD internal FIFOs
--
-- These are used to help with reaching timing closure with slow signals
-- such as ddr_cmd_full, by decoupling them from the rest of the FPGA.
------------------------------------------------------------------------------
-- Burst counter
p_ddr_burst_cnt : process (wb_clk_i)
--
-- CMD FIFO and control
--
cmp_cmd_fifo : entity work.generic_sync_fifo
generic map (
g_DATA_WIDTH => c_CMD_FIFO_WIDTH,
g_SIZE => c_CMD_FIFO_DEPTH,
g_SHOW_AHEAD => TRUE,
g_SHOW_AHEAD_LEGACY_MODE => FALSE)
port map (
rst_n_i => wb_rst_n_i,
clk_i => wb_clk_i,
d_i => cmd_fifo_din,
we_i => cmd_fifo_we,
q_o => cmd_fifo_dout,
rd_i => cmd_fifo_rd,
empty_o => cmd_fifo_empty,
full_o => cmd_fifo_full);
cmd_fifo_din <= ddr_cmd_byte_addr & ddr_cmd_instr & ddr_cmd_bl;
cmd_fifo_we <= ddr_cmd_en;
ddr_cmd_en_out <= cmd_fifo_rd;
ddr_cmd_bl_o <= cmd_fifo_dout(5 downto 0);
ddr_cmd_instr_o <= cmd_fifo_dout(8 downto 6);
ddr_cmd_byte_addr_o <= cmd_fifo_dout(c_CMD_FIFO_WIDTH-1 downto 9);
ddr_cmd_en_o <= ddr_cmd_en_out;
ddr_cmd_clk_o <= wb_clk_i;
-- We need to make sure that there is always a delay between consecutive commands,
-- otherwise the cmp_cmd_fifo above can queue up several write commands, and
-- release them immediately one after the other, causing the MCB's WR FIFO to
-- underrun.
p_cmd_fifo_rd_monostable : process (wb_clk_i) is
variable cmd_fifo_rd_timer : unsigned(5 downto 0) := (others => '0');
begin
if rising_edge(wb_clk_i) then
if (rst_n_i = '0') then
ddr_burst_cnt <= (others => '0');
if wb_rst_n_i = '0' then
cmd_fifo_rd_disable <= '0';
else
if (wb_cyc_f_edge = '1') then
ddr_burst_cnt <= to_unsigned(0, ddr_burst_cnt'length);
elsif (wb_stb_valid = '1') then
if (ddr_burst_cnt = c_DDR_BURST_LENGTH) then
ddr_burst_cnt <= to_unsigned(1, ddr_burst_cnt'length);
else
ddr_burst_cnt <= ddr_burst_cnt + 1;
if cmd_fifo_rd = '1' then
cmd_fifo_rd_timer := to_unsigned(c_DDR_BURST_LEN, cmd_fifo_rd_timer'length);
cmd_fifo_rd_disable <= '1';
elsif cmd_fifo_rd_disable <= '1' then
cmd_fifo_rd_timer := cmd_fifo_rd_timer - 1;
if cmd_fifo_rd_timer = 0 then
cmd_fifo_rd_disable <= '0';
end if;
elsif (ddr_burst_cnt = c_DDR_BURST_LENGTH) then
ddr_burst_cnt <= to_unsigned(0, ddr_burst_cnt'length);
end if;
end if;
end if;
end process p_ddr_burst_cnt;
-- Read enable signal generation
ddr_rd_en <= not(ddr_rd_empty_i);
end process p_cmd_fifo_rd_monostable;
-- Data output and ack
p_ddr_outputs : process (wb_clk_i)
p_cmd_fifo_rd : process (cmd_fifo_dout(6 downto 0), cmd_fifo_empty,
cmd_fifo_rd_disable, ddr_cmd_full_i,
ddr_wr_count_i) is
variable next_cmd_len : unsigned(6 downto 0) := (others => '0');
variable wr_fifo_cnt : unsigned(6 downto 0) := (others => '0');
begin
if rising_edge(wb_clk_i) then
if (rst_n_i = '0') then
wb_ack_o <= '0';
wb_data_o <= (others => '0');
else
-- Generates ack signal
if (ddr_rd_en = '1') or (ddr_wr_en = '1') then
wb_ack_o <= '1';
else
wb_ack_o <= '0';
end if;
-- Registered data output
wb_data_o <= ddr_rd_data_i;
cmd_fifo_rd <= '0';
if cmd_fifo_empty = '0' and ddr_cmd_full_i = '0' and cmd_fifo_rd_disable = '0' then
next_cmd_len := unsigned('0' & cmd_fifo_dout(5 downto 0));
wr_fifo_cnt := unsigned(ddr_wr_count_i);
if cmd_fifo_dout(6) = '1' or wr_fifo_cnt > next_cmd_len then
cmd_fifo_rd <= '1';
end if;
end if;
end process p_ddr_outputs;
end process p_cmd_fifo_rd;
--
-- WR FIFO and control
--
cmp_wr_fifo : entity work.generic_sync_fifo
generic map (
g_DATA_WIDTH => c_WR_FIFO_WIDTH,
g_SIZE => c_WR_FIFO_DEPTH,
g_SHOW_AHEAD => TRUE,
g_SHOW_AHEAD_LEGACY_MODE => FALSE)
port map (
rst_n_i => wb_rst_n_i,
clk_i => wb_clk_i,
d_i => wr_fifo_din,
we_i => wr_fifo_we,
q_o => wr_fifo_dout,
rd_i => wr_fifo_rd,
empty_o => wr_fifo_empty,
full_o => wr_fifo_full);
-- Write to the Write FIFO of the DDR if there is a valid WB write cycle
-- and we are not stalling (in which case we should not write the same data
-- multiple times).
wr_fifo_we <= wb_stb_valid and wb_we_i and not (wr_fifo_full or cmd_fifo_full);
wr_fifo_din <= (not wb_sel_i) & wb_data_i;
wr_fifo_rd <= not (wr_fifo_empty or ddr_wr_full_i);
ddr_wr_en <= wr_fifo_rd;
ddr_wr_mask_o <= wr_fifo_dout(c_WR_FIFO_WIDTH-1 downto g_DATA_PORT_SIZE);
ddr_wr_data_o <= wr_fifo_dout(g_DATA_PORT_SIZE-1 downto 0);
ddr_wr_en_o <= ddr_wr_en;
ddr_wr_clk_o <= wb_clk_i;
--
-- RD FIFO and control
--
cmp_rd_fifo : entity work.generic_sync_fifo
generic map (
g_DATA_WIDTH => c_RD_FIFO_WIDTH,
g_SIZE => c_RD_FIFO_DEPTH,
g_SHOW_AHEAD => FALSE)
port map (
rst_n_i => wb_rst_n_i,
clk_i => wb_clk_i,
d_i => rd_fifo_din,
we_i => rd_fifo_we,
q_o => rd_fifo_dout,
rd_i => rd_fifo_rd,
empty_o => rd_fifo_empty,
full_o => rd_fifo_full);
rd_fifo_din <= ddr_rd_data_i;
rd_fifo_we <= not (ddr_rd_empty_i or rd_fifo_full);
-- If there is data to be read from the Read FIFO of the DDR, it is safe to
-- assume that it is the result of a valid WB read cycle earlier. As long as
-- the WB cycle is still ongoing, we should output the data, even if currently
-- the slave is stalling.
rd_fifo_rd <= wb_cyc_i and not rd_fifo_empty;
ddr_rd_en_o <= rd_fifo_we;
ddr_rd_clk_o <= wb_clk_i;
-- Stall signal output
p_ddr_stall : process (wb_clk_i)
------------------------------------------------------------------------------
-- Pipelined WB slave
------------------------------------------------------------------------------
wb_stb_valid <= wb_cyc_i and wb_stb_i;
-- The slave will stall under any of the two following conditions:
-- 1. When the DDR Command FIFO is full and there is an active WB cycle.
-- 2. When the DDR Write FIFO is full and there is an active WB *write* cycle.
wb_stall <= wb_stb_valid and (cmd_fifo_full or (wb_we_i and wr_fifo_full));
-- Whenever we read/write something from/to the Read/Write FIFOs
-- of the DDR we assert ACK.
p_wb_ack : process (wb_clk_i) is
begin
if rising_edge(wb_clk_i) then
if (rst_n_i = '0') then
wb_stall_o <= '0';
else
if ((ddr_wr_count_i > c_FIFO_ALMOST_FULL) or
(ddr_wr_full_i = '1') or
(ddr_rd_count_i > c_FIFO_ALMOST_FULL) or
(ddr_rd_full_i = '1')) then
wb_stall_o <= '1';
else
wb_stall_o <= '0';
end if;
end if;
wb_ack_o <= wr_fifo_we or rd_fifo_rd;
end if;
end process p_ddr_stall;
--wb_stall_o <= ddr_cmd_full_i or ddr_wr_full_i or ddr_rd_full_i;
end process p_wb_ack;
wb_data_o <= rd_fifo_dout;
wb_stall_o <= wb_stall;
-- Assign outputs
ddr_cmd_en_o <= ddr_cmd_en;
ddr_cmd_instr_o <= ddr_cmd_instr;
ddr_cmd_bl_o <= ddr_cmd_bl;
ddr_cmd_byte_addr_o <= ddr_cmd_byte_addr;
------------------------------------------------------------------------------
-- DDR Command FIFO control FSM
------------------------------------------------------------------------------
ddr_wr_en_o <= ddr_wr_en;
ddr_wr_mask_o <= ddr_wr_mask;
ddr_wr_data_o <= ddr_wr_data;
-- This FSM controls the generation of the 'cmd_byte_addr', 'cmd_en',
-- 'cmd_instr' and 'cmd_bl' signals.
p_cmd_fsm : process (wb_clk_i) is
variable ddr_burst_cnt : unsigned(5 downto 0) := (others => '0');
variable next_cmd_instr : std_logic := '0';
variable next_cmd_addr : std_logic_vector(31 downto 0) := (others => '0');
ddr_rd_en_o <= ddr_rd_en;
begin
if rising_edge(wb_clk_i) then
if wb_rst_n_i = '0' then
cmd_fsm_state <= S_IDLE;
ddr_cmd_instr <= (others => '0');
ddr_cmd_byte_addr <= (others => '0');
ddr_cmd_bl <= (others => '0');
ddr_burst_cnt := (others => '0');
else
case cmd_fsm_state is
when S_IDLE =>
ddr_cmd_en <= '0';
if wb_stb_valid = '1' and wb_stall = '0' then
ddr_burst_cnt := to_unsigned(1, 6);
next_cmd_instr := not wb_we_i;
next_cmd_addr := wb_addr_i;
cmd_fsm_state <= S_BUILD_BURST;
end if;
when S_BUILD_BURST =>
ddr_cmd_en <= '0';
if wb_stb_valid = '1' and wb_stall = '0' then
ddr_burst_cnt := ddr_burst_cnt + 1;
end if;
-- Bursts are dispathced when:
-- 1: We reach the burst length limit.
-- 2: We are in a read cycle and STB is de-asserted.
-- 3: We are in a write cycle and CYC is de-asserted.
if (ddr_burst_cnt = to_unsigned(c_DDR_BURST_LEN, 6) or
(wb_stb_valid = '0' and next_cmd_instr = '1') or
(wb_cyc_i = '0' and next_cmd_instr = '0')) then
ddr_cmd_byte_addr <= f_align_addr(next_cmd_addr);
ddr_cmd_instr(0) <= next_cmd_instr;
if (ddr_burst_cnt = to_unsigned(c_DDR_BURST_LEN, 6)) then
ddr_cmd_bl <= "001111";
else
ddr_cmd_bl <= std_logic_vector(ddr_burst_cnt - 1);
end if;
cmd_fsm_state <= S_EXEC_BURST;
end if;
when S_EXEC_BURST =>
if cmd_fifo_full = '0' then
ddr_cmd_en <= '1';
-- Check if we need to start another burst or not.
if wb_stb_valid = '1' and wb_stall = '0' then
ddr_burst_cnt := to_unsigned(1, 6);
next_cmd_instr := not wb_we_i;
next_cmd_addr := wb_addr_i;
cmd_fsm_state <= S_BUILD_BURST;
else
cmd_fsm_state <= S_IDLE;
end if;
end if;
when others =>
cmd_fsm_state <= S_IDLE;
end case;
end if;
end if;
end process p_cmd_fsm;
end architecture rtl;
--==============================================================================
--! Architecure end
--==============================================================================
end architecture arch;
hdl/rtl/ddr3_ctrl_wb_single.vhd deleted 100644 → 0
View file @ bb5b8f75
--==============================================================================
--! @file ddr3_ctrl_wb_single.vhd
--==============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- DDR3 Controller Wishbone Interface (single access only)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--! @brief
--! DDR3 Controller Wishbone Interface
--------------------------------------------------------------------------------
--! @details
--! Wishbone interface for DDR3 controller.
--------------------------------------------------------------------------------
--! @version
--! 0.1 | mc | 14.07.2011 | File creation and Doxygen comments
--!
--! @author
--! mc : Matthieu Cattin, CERN (BE-CO-HT)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--==============================================================================
--! Entity declaration for ddr3_ctrl_wb
--==============================================================================
entity ddr3_ctrl_wb is
generic(
--! DDR3 byte address width
g_BYTE_ADDR_WIDTH : integer := 30;
--! Data mask size (8-bit granularity)
g_MASK_SIZE : integer := 4;
--! Data width
g_DATA_PORT_SIZE : integer := 32
);
port(
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
ddr_cmd_clk_o : out std_logic;
ddr_cmd_en_o : out std_logic;
ddr_cmd_instr_o : out std_logic_vector(2 downto 0);
ddr_cmd_bl_o : out std_logic_vector(5 downto 0);
ddr_cmd_byte_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
ddr_cmd_empty_i : in std_logic;
ddr_cmd_full_i : in std_logic;
ddr_wr_clk_o : out std_logic;
ddr_wr_en_o : out std_logic;
ddr_wr_mask_o : out std_logic_vector(g_MASK_SIZE - 1 downto 0);
ddr_wr_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
ddr_wr_full_i : in std_logic;
ddr_wr_empty_i : in std_logic;
ddr_wr_count_i : in std_logic_vector(6 downto 0);
ddr_wr_underrun_i : in std_logic;
ddr_wr_error_i : in std_logic;
ddr_rd_clk_o : out std_logic;
ddr_rd_en_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
ddr_rd_full_i : in std_logic;
ddr_rd_empty_i : in std_logic;
ddr_rd_count_i : in std_logic_vector(6 downto 0);
ddr_rd_overflow_i : in std_logic;
ddr_rd_error_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(g_BYTE_ADDR_WIDTH - 3 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic
);
end entity ddr3_ctrl_wb;
--==============================================================================
--! Architecure declaration for ddr3_ctrl_wb
--==============================================================================
architecture rtl of ddr3_ctrl_wb is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_DDR_BURST_LENGTH : integer := 32; -- must not exceed 63
constant c_FIFO_ALMOST_FULL : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(57, 7));
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type t_wb_fsm_states is (WB_IDLE, WB_WRITE, WB_READ, WB_READ_WAIT);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal rst_n : std_logic;
signal wb_fsm_state : t_wb_fsm_states := WB_IDLE;
signal ddr_burst_cnt : unsigned(5 downto 0);
signal ddr_cmd_en : std_logic;
signal ddr_cmd_en_d : std_logic;
signal ddr_cmd_en_r_edge : std_logic;
signal ddr_cmd_instr : std_logic_vector(2 downto 0);
signal ddr_cmd_bl : std_logic_vector(5 downto 0);
signal ddr_cmd_byte_addr : std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
signal ddr_wr_en : std_logic;
signal ddr_wr_mask : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal ddr_wr_data : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal ddr_rd_en : std_logic;
--==============================================================================
--! Architecure begin
--==============================================================================
begin
------------------------------------------------------------------------------
-- Wishbone interface
------------------------------------------------------------------------------
-- Reset sync to wishbone clock
p_rst_sync : process (rst_n_i, wb_clk_i)
begin
if (rst_n_i = '0') then
rst_n <= '0';
elsif rising_edge(wb_clk_i) then
rst_n <= '1';
end if;
end process p_rst_sync;
-- Clocking
ddr_cmd_clk_o <= wb_clk_i;
ddr_wr_clk_o <= wb_clk_i;
ddr_rd_clk_o <= wb_clk_i;
p_wb_interface : process (wb_clk_i)
begin
if (rising_edge(wb_clk_i)) then
if (rst_n = '0') then
wb_fsm_state <= WB_IDLE;
wb_ack_o <= '0';
wb_data_o <= (others => '0');
--wb_stall_o <= '0';
ddr_cmd_en <= '0';
ddr_cmd_byte_addr <= (others => '0');
ddr_cmd_bl <= (others => '0');
ddr_cmd_instr <= (others => '0');
ddr_wr_data <= (others => '0');
ddr_wr_mask <= (others => '0');
ddr_wr_en <= '0';
ddr_rd_en <= '0';
else
case wb_fsm_state is
when WB_IDLE =>
if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then
-- Write from wishbone
ddr_rd_en <= '0';
wb_ack_o <= '0';
ddr_cmd_en <= '0';
ddr_cmd_instr <= "000";
ddr_cmd_bl <= "000000";
ddr_cmd_byte_addr <= wb_addr_i & "00";
ddr_wr_mask <= "0000";
ddr_wr_data <= wb_data_i;
ddr_wr_en <= '1';
wb_fsm_state <= WB_WRITE;
elsif (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '0') then
-- Read from wishbone
ddr_wr_en <= '0';
wb_ack_o <= '0';
ddr_cmd_en <= '0';
ddr_cmd_instr <= "001";
ddr_cmd_bl <= "000000";
ddr_cmd_byte_addr <= wb_addr_i & "00";
wb_fsm_state <= WB_READ;
else
wb_ack_o <= '0';
ddr_cmd_en <= '0';
ddr_wr_en <= '0';
ddr_rd_en <= '0';
end if;
when WB_WRITE =>
wb_ack_o <= '1';
ddr_wr_en <= '0';
ddr_cmd_en <= '1';
wb_fsm_state <= WB_IDLE;
when WB_READ =>
ddr_cmd_en <= '1';
wb_fsm_state <= WB_READ_WAIT;
when WB_READ_WAIT =>
ddr_cmd_en <= '0';
ddr_rd_en <= not(ddr_rd_empty_i);
wb_ack_o <= ddr_rd_en;
wb_data_o <= ddr_rd_data_i;
if (ddr_rd_en = '1') then
wb_fsm_state <= WB_IDLE;
end if;
when others => null;
end case;
end if;
end if;
end process p_wb_interface;
-- Port 1 pipelined mode compatibility
wb_stall_o <= ddr_cmd_full_i or ddr_wr_full_i or ddr_rd_full_i;
-- Assign outputs
ddr_cmd_en_o <= ddr_cmd_en;
ddr_cmd_instr_o <= ddr_cmd_instr;
ddr_cmd_bl_o <= ddr_cmd_bl;
ddr_cmd_byte_addr_o <= ddr_cmd_byte_addr;
ddr_wr_en_o <= ddr_wr_en;
ddr_wr_mask_o <= ddr_wr_mask;
ddr_wr_data_o <= ddr_wr_data;
ddr_rd_en_o <= ddr_rd_en;
end architecture rtl;
--==============================================================================
--! Architecure end
--==============================================================================
hdl/testbench/.gitignore 0 → 100644
View file @ 70f9de31
work/
NullFile
Makefile
modelsim.ini
transcript*
*.wlf
wlf*
buildinfo_pkg.vhd
hdl/testbench/Manifest.py 0 → 100644
View file @ 70f9de31
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
# Use fetchto to point to parent folder of general-cores, like this:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../"
include_dirs = [
fetchto + "/general-cores/sim",
]
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../",
fetchto + "/general-cores",
],
}
ctrls = ["bank3_32b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/main.sv 0 → 100644
View file @ 70f9de31
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// DDR3 Controller for Xilinx Spartan6
// http://www.ohwr.org/projects/ddr3-sp6-core
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: Testbench for the Xilinx Spartan-6 DDR3 Controller.
//
//------------------------------------------------------------------------------
// Copyright CERN 2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ns/1ps
`include "if_wb_master.svh"
module main;
reg clk_333m = 0;
reg clk_125m = 0;
always #1.5ns clk_333m <= ~clk_333m;
always #4.0ns clk_125m <= ~clk_125m;
wire ddr_cas_n, ddr_ck_p, ddr_ck_n, ddr_cke;
wire [1:0] ddr_dm, ddr_dqs_p, ddr_dqs_n;
wire ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n;
wire [15:0] ddr_dq;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_rzq;
logic rst_n;
IWishboneMaster I_wb (clk_125m, rst_n);
//---------------------------------------------------------------------------
// The DUT
//---------------------------------------------------------------------------
ddr3_ctrl #
(
.g_RST_ACT_LOW (1),
.g_SIMULATION ("TRUE"),
.g_CALIB_SOFT_IP ("FALSE")
)
DUT
(
.clk_i (clk_333m),
.rst_n_i (rst_n),
.ddr3_dq_b (ddr_dq),
.ddr3_a_o (ddr_a),
.ddr3_ba_o (ddr_ba),
.ddr3_ras_n_o (ddr_ras_n),
.ddr3_cas_n_o (ddr_cas_n),
.ddr3_we_n_o (ddr_we_n),
.ddr3_odt_o (ddr_odt),
.ddr3_rst_n_o (ddr_reset_n),
.ddr3_cke_o (ddr_cke),
.ddr3_dm_o (ddr_dm[0]),
.ddr3_udm_o (ddr_dm[1]),
.ddr3_dqs_p_b (ddr_dqs_p[0]),
.ddr3_dqs_n_b (ddr_dqs_n[0]),
.ddr3_udqs_p_b (ddr_dqs_p[1]),
.ddr3_udqs_n_b (ddr_dqs_n[1]),
.ddr3_clk_p_o (ddr_ck_p),
.ddr3_clk_n_o (ddr_ck_n),
.ddr3_rzq_b (ddr_rzq),
.wb0_rst_n_i (rst_n),
.wb0_clk_i (clk_125m),
.wb0_sel_i (I_wb.sel),
.wb0_cyc_i (I_wb.cyc),
.wb0_stb_i (I_wb.stb),
.wb0_we_i (I_wb.we),
.wb0_addr_i (I_wb.adr),
.wb0_data_i (I_wb.dat_o),
.wb0_data_o (I_wb.dat_i),
.wb0_ack_o (I_wb.ack),
.wb0_stall_o (I_wb.stall)
);
//---------------------------------------------------------------------------
// DDR memory model
//---------------------------------------------------------------------------
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
DDR_MEM
(
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs (ddr_dm),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs (ddr_dqs_p),
.dqs_n (ddr_dqs_n),
.tdqs_n (),
.odt (ddr_odt)
);
CWishboneAccessor acc;
wb_cycle_t c,r;
wb_xfer_t x;
const int c_NPACKETS = 2000;
const int c_DDR_BURST = 16;
const int c_ADDR_BASE = 'h0000;
const int c_DATA_BASE = 1;
task rw_test;
input int word_count;
begin
int i;
time wr_t, rd_t;
$display("- Begin write test (%0d bytes)", word_count * 4);
c.ctype = PIPELINED;
c.rw = 1;
c.data.delete();
for (i = 0; i < word_count; i++) begin
x.a = c_ADDR_BASE + 4*i;
x.d = c_DATA_BASE + i;
x.size = 4;
c.data.push_back(x);
end
wr_t = $time;
acc.put(c);
acc.get(r);
wr_t = $time - wr_t;
$display(" %0d bytes written to DDR in %0t (%0.2f MB/s)",
word_count * 4, wr_t, 1e3 * word_count * 4.0 / wr_t);
wait (DUT.p0_wr_empty == 1);
// Perform read test of 8x full bursts
$display("- Begin read test (%0d bytes)", word_count * 4);
c.ctype = PIPELINED;
c.rw = 0;
c.data.delete();
for (i = 0; i < word_count; i++) begin
x.a = c_ADDR_BASE + 4*i;
x.size = 4;
c.data.push_back(x);
end
rd_t = $time;
acc.put(c);
acc.get(r);
rd_t = $time - rd_t;
$display(" %0d bytes read back from DDR in %0t (%0.2f MB/s)",
word_count * 4, rd_t, 1e3 * word_count * 4.0 / rd_t);
$display("- Data verification");
for (i = 0; i < word_count; i++) begin
if (r.data[i].d != c_DATA_BASE + i)
$fatal(1, "Read-back error at address %8x. Expected %8x, but got %8x instead",
r.data[i].a, c_DATA_BASE + i, r.data[i].d);
end
$display(" done");
end
endtask // rw_test
initial begin
int i;
$timeformat (-6, 3, "us", 10);
$display();
$display("-------------------");
$display("Start of simulation");
$display("-------------------");
$display();
rst_n = 1'b0;
#1us;
rst_n = 1'b1;
acc = I_wb.get_accessor();
wait (DUT.p0_wr_full == 0);
#1us;
// Perform write/read-back test of 8x full bursts
rw_test(c_DDR_BURST * 8);
#5us;
// Check from 1 to c_DDR_BURST -2
for (i = 1; i < c_DDR_BURST - 1; i++)
begin
rw_test(i);
#5us;
end
// Check in multiples of c_DDR_BURST, including -1 and +1 of c_DDR_BURST
// for corner cases.
for (i= 1; i < 8; i++)
begin
rw_test(i*c_DDR_BURST - 1);
#5us;
rw_test(i*c_DDR_BURST);
#5us;
rw_test(i*c_DDR_BURST + 1);
#5us;
end
// Perform long write/read-back test
rw_test(c_NPACKETS);
#1us;
$display();
$display("-------------------");
$display("Simulation PASSED");
$display("-------------------");
$display();
$finish;
end
endmodule // main
hdl/testbench/run.do 0 → 100644
View file @ 70f9de31
vsim -voptargs=+acc -quiet -t 10fs -L unisim -L secureip work.main -suppress 8822,8617,8683,8684
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
hdl/testbench/run_ci.do 0 → 100644
View file @ 70f9de31
vsim -voptargs=+acc=lprn -quiet -t 10fs -L unisim -L secureip work.main -suppress 8822,8617,8683,8684
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
run -all
hdl/testbench/wave.do 0 → 100644
View file @ 70f9de31
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_ddr3_ctrl_wb_0/rst_n_i
add wave -noupdate /main/DUT/cmp_ddr3_ctrl_wb_0/wb_clk_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_stb_valid
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_addr_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_sel_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_stall_o
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_ack_o
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_data_o
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_data_i
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fsm_state
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/ddr_burst_cnt
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/next_cmd_instr
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/next_cmd_bl
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/next_cmd_addr
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_we
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_full
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_empty
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_din
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_dout
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_rd_disable
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fifo_rd/next_cmd_len
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fifo_rd/wr_fifo_cnt
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_rd
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_full_i
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_count_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_empty_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_error_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_full_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_overflow_i
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_we
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_full
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_empty
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_din
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_dout
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_rd
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_full_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_empty_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_count_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_underrun_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_error_i
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dq_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_a_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_ba_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_ras_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_cas_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_we_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_odt_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_rst_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_cke_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dm_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_udm_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dqs_p_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dqs_n_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_udqs_p_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_udqs_n_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_clk_p_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_clk_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_rzq_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_zio_b
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2321230250 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 336
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 400000
configure wave -gridperiod 800000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1623922490 fs} {3479833910 fs}
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