Commit 70f9de31 authored by Dimitris Lampridis's avatar Dimitris Lampridis

Merge branch 'release/2.0.0'

parents bb5b8f75 e56167a1
..
SPDX-License-Identifier: CC0-1.0
SPDX-FileCopyrightText: 2019-2020 CERN
==========
Change Log
==========
- Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
- Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
2.0.0 - 2020-07-24
=================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v2.0.0
Added
-----
- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench
Changed
-------
- Complete rewrite of the Wishbone interface to improve compatibility, performance and code readability
Removed
-------
- Unused file ``rtl/ddr3_ctrl_wb_single.vhd``
1.0.0 - 2016-05-19
==================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v1.0.0
Added
-----
- First release
Creative Commons Legal Code
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4. Limitations and Disclaimers.
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......@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-07-13
-- Last update: 2018-11-12
-- Last update: 2020-07-07
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Wishbone to DDR3 interface for Xilinx FPGA with MCB (Memory
......@@ -59,6 +59,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--! Specific packages
use work.wishbone_pkg.all;
--==============================================================================
--! Entity declaration for ddr3_ctrl
......@@ -90,12 +91,16 @@ entity ddr3_ctrl is
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Port 0 address granularity
g_P0_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
g_P1_BYTE_ADDR_WIDTH : integer := 30;
--! Port 0 address granularity
g_P1_ADDR_GRANULARITY : t_wishbone_address_granularity := WORD
);
port(
......@@ -333,9 +338,10 @@ begin
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wb_0 : entity work.ddr3_ctrl_wb
generic map(
g_BYTE_ADDR_WIDTH => g_P0_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P0_MASK_SIZE,
g_DATA_PORT_SIZE => g_P0_DATA_PORT_SIZE
g_BYTE_ADDR_WIDTH => g_P0_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P0_MASK_SIZE,
g_DATA_PORT_SIZE => g_P0_DATA_PORT_SIZE,
g_ADDR_GRANULARITY => g_P0_ADDR_GRANULARITY
)
port map(
rst_n_i => wb0_rst_n_i,
......@@ -363,6 +369,7 @@ begin
ddr_rd_count_i => p0_rd_count,
ddr_rd_overflow_i => p0_rd_overflow,
ddr_rd_error_i => p0_rd_error,
wb_rst_n_i => wb0_rst_n_i,
wb_clk_i => wb0_clk_i,
wb_sel_i => wb0_sel_i,
wb_cyc_i => wb0_cyc_i,
......@@ -380,9 +387,10 @@ begin
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wb_1 : entity work.ddr3_ctrl_wb
generic map(
g_BYTE_ADDR_WIDTH => g_P1_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P1_MASK_SIZE,
g_DATA_PORT_SIZE => g_P1_DATA_PORT_SIZE
g_BYTE_ADDR_WIDTH => g_P1_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P1_MASK_SIZE,
g_DATA_PORT_SIZE => g_P1_DATA_PORT_SIZE,
g_ADDR_GRANULARITY => g_P1_ADDR_GRANULARITY
)
port map(
rst_n_i => wb1_rst_n_i,
......@@ -410,6 +418,7 @@ begin
ddr_rd_count_i => p1_rd_count,
ddr_rd_overflow_i => p1_rd_overflow,
ddr_rd_error_i => p1_rd_error,
wb_rst_n_i => wb1_rst_n_i,
wb_clk_i => wb1_clk_i,
wb_sel_i => wb1_sel_i,
wb_cyc_i => wb1_cyc_i,
......
This diff is collapsed.
This diff is collapsed.
work/
NullFile
Makefile
modelsim.ini
transcript*
*.wlf
wlf*
buildinfo_pkg.vhd
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
# Use fetchto to point to parent folder of general-cores, like this:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../../"
include_dirs = [
fetchto + "/general-cores/sim",
]
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../",
fetchto + "/general-cores",
],
}
ctrls = ["bank3_32b_32b"]
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// DDR3 Controller for Xilinx Spartan6
// http://www.ohwr.org/projects/ddr3-sp6-core
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: Testbench for the Xilinx Spartan-6 DDR3 Controller.
//
//------------------------------------------------------------------------------
// Copyright CERN 2019
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
`timescale 1ns/1ps
`include "if_wb_master.svh"
module main;
reg clk_333m = 0;
reg clk_125m = 0;
always #1.5ns clk_333m <= ~clk_333m;
always #4.0ns clk_125m <= ~clk_125m;
wire ddr_cas_n, ddr_ck_p, ddr_ck_n, ddr_cke;
wire [1:0] ddr_dm, ddr_dqs_p, ddr_dqs_n;
wire ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n;
wire [15:0] ddr_dq;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_rzq;
logic rst_n;
IWishboneMaster I_wb (clk_125m, rst_n);
//---------------------------------------------------------------------------
// The DUT
//---------------------------------------------------------------------------
ddr3_ctrl #
(
.g_RST_ACT_LOW (1),
.g_SIMULATION ("TRUE"),
.g_CALIB_SOFT_IP ("FALSE")
)
DUT
(
.clk_i (clk_333m),
.rst_n_i (rst_n),
.ddr3_dq_b (ddr_dq),
.ddr3_a_o (ddr_a),
.ddr3_ba_o (ddr_ba),
.ddr3_ras_n_o (ddr_ras_n),
.ddr3_cas_n_o (ddr_cas_n),
.ddr3_we_n_o (ddr_we_n),
.ddr3_odt_o (ddr_odt),
.ddr3_rst_n_o (ddr_reset_n),
.ddr3_cke_o (ddr_cke),
.ddr3_dm_o (ddr_dm[0]),
.ddr3_udm_o (ddr_dm[1]),
.ddr3_dqs_p_b (ddr_dqs_p[0]),
.ddr3_dqs_n_b (ddr_dqs_n[0]),
.ddr3_udqs_p_b (ddr_dqs_p[1]),
.ddr3_udqs_n_b (ddr_dqs_n[1]),
.ddr3_clk_p_o (ddr_ck_p),
.ddr3_clk_n_o (ddr_ck_n),
.ddr3_rzq_b (ddr_rzq),
.wb0_rst_n_i (rst_n),
.wb0_clk_i (clk_125m),
.wb0_sel_i (I_wb.sel),
.wb0_cyc_i (I_wb.cyc),
.wb0_stb_i (I_wb.stb),
.wb0_we_i (I_wb.we),
.wb0_addr_i (I_wb.adr),
.wb0_data_i (I_wb.dat_o),
.wb0_data_o (I_wb.dat_i),
.wb0_ack_o (I_wb.ack),
.wb0_stall_o (I_wb.stall)
);
//---------------------------------------------------------------------------
// DDR memory model
//---------------------------------------------------------------------------
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
DDR_MEM
(
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs (ddr_dm),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs (ddr_dqs_p),
.dqs_n (ddr_dqs_n),
.tdqs_n (),
.odt (ddr_odt)
);
CWishboneAccessor acc;
wb_cycle_t c,r;
wb_xfer_t x;
const int c_NPACKETS = 2000;
const int c_DDR_BURST = 16;
const int c_ADDR_BASE = 'h0000;
const int c_DATA_BASE = 1;
task rw_test;
input int word_count;
begin
int i;
time wr_t, rd_t;
$display("- Begin write test (%0d bytes)", word_count * 4);
c.ctype = PIPELINED;
c.rw = 1;
c.data.delete();
for (i = 0; i < word_count; i++) begin
x.a = c_ADDR_BASE + 4*i;
x.d = c_DATA_BASE + i;
x.size = 4;
c.data.push_back(x);
end
wr_t = $time;
acc.put(c);
acc.get(r);
wr_t = $time - wr_t;
$display(" %0d bytes written to DDR in %0t (%0.2f MB/s)",
word_count * 4, wr_t, 1e3 * word_count * 4.0 / wr_t);
wait (DUT.p0_wr_empty == 1);
// Perform read test of 8x full bursts
$display("- Begin read test (%0d bytes)", word_count * 4);
c.ctype = PIPELINED;
c.rw = 0;
c.data.delete();
for (i = 0; i < word_count; i++) begin
x.a = c_ADDR_BASE + 4*i;
x.size = 4;
c.data.push_back(x);
end
rd_t = $time;
acc.put(c);
acc.get(r);
rd_t = $time - rd_t;
$display(" %0d bytes read back from DDR in %0t (%0.2f MB/s)",
word_count * 4, rd_t, 1e3 * word_count * 4.0 / rd_t);
$display("- Data verification");
for (i = 0; i < word_count; i++) begin
if (r.data[i].d != c_DATA_BASE + i)
$fatal(1, "Read-back error at address %8x. Expected %8x, but got %8x instead",
r.data[i].a, c_DATA_BASE + i, r.data[i].d);
end
$display(" done");
end
endtask // rw_test
initial begin
int i;
$timeformat (-6, 3, "us", 10);
$display();
$display("-------------------");
$display("Start of simulation");
$display("-------------------");
$display();
rst_n = 1'b0;
#1us;
rst_n = 1'b1;
acc = I_wb.get_accessor();
wait (DUT.p0_wr_full == 0);
#1us;
// Perform write/read-back test of 8x full bursts
rw_test(c_DDR_BURST * 8);
#5us;
// Check from 1 to c_DDR_BURST -2
for (i = 1; i < c_DDR_BURST - 1; i++)
begin
rw_test(i);
#5us;
end
// Check in multiples of c_DDR_BURST, including -1 and +1 of c_DDR_BURST
// for corner cases.
for (i= 1; i < 8; i++)
begin
rw_test(i*c_DDR_BURST - 1);
#5us;
rw_test(i*c_DDR_BURST);
#5us;
rw_test(i*c_DDR_BURST + 1);
#5us;
end
// Perform long write/read-back test
rw_test(c_NPACKETS);
#1us;
$display();
$display("-------------------");
$display("Simulation PASSED");
$display("-------------------");
$display();
$finish;
end
endmodule // main
vsim -voptargs=+acc -quiet -t 10fs -L unisim -L secureip work.main -suppress 8822,8617,8683,8684
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
vsim -voptargs=+acc=lprn -quiet -t 10fs -L unisim -L secureip work.main -suppress 8822,8617,8683,8684
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
run -all
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_ddr3_ctrl_wb_0/rst_n_i
add wave -noupdate /main/DUT/cmp_ddr3_ctrl_wb_0/wb_clk_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_stb_valid
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_addr_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_sel_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_stall_o
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_ack_o
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_data_o
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate -expand -group Wishbone /main/DUT/cmp_ddr3_ctrl_wb_0/wb_data_i
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fsm_state
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/ddr_burst_cnt
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/next_cmd_instr
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/next_cmd_bl
add wave -noupdate -expand -group {CMD port} -color Magenta /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fsm/next_cmd_addr
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_we
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_full
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_empty
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_din
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_dout
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_rd_disable
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fifo_rd/next_cmd_len
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/p_cmd_fifo_rd/wr_fifo_cnt
add wave -noupdate -expand -group {CMD port} -color Thistle /main/DUT/cmp_ddr3_ctrl_wb_0/cmd_fifo_rd
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_full_i
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o
add wave -noupdate -expand -group {CMD port} -color {Blue Violet} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_count_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_empty_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_error_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_full_i
add wave -noupdate -expand -group {RD port} -color Turquoise /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_rd_overflow_i
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_we
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_full
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_empty
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_din
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_dout
add wave -noupdate -expand -group {WR port} -color Wheat /main/DUT/cmp_ddr3_ctrl_wb_0/wr_fifo_rd
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_full_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_empty_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_count_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_underrun_i
add wave -noupdate -expand -group {WR port} -color {Indian Red} /main/DUT/cmp_ddr3_ctrl_wb_0/ddr_wr_error_i
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dq_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_a_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_ba_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_ras_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_cas_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_we_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_odt_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_rst_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_cke_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dm_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_udm_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dqs_p_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_dqs_n_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_udqs_p_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_udqs_n_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_clk_p_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_clk_n_o
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_rzq_b
add wave -noupdate -group {DDR interface} /main/DUT/ddr3_zio_b
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2321230250 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 336
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 400000
configure wave -gridperiod 800000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1623922490 fs} {3479833910 fs}
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