Bypass IBUFG in generated cores to avoid translation errors.

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@106 739e5516-d4a2-47df-ba96-5610c1fa693f

Bypass IBUFG in generated cores to avoid translation errors.
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@106 739e5516-d4a2-47df-ba96-5610c1fa693f
59af43bc · mcattin · f28c1900 · 59af43bc · 59af43bc · 59af43bc
Commit 59af43bc authored Jul 16, 2012 by mcattin
6 changed files
--- a/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/memc4_infrastructure.vhd
+++ b/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/memc4_infrastructure.vhd
@@ -165,11 +165,12 @@ begin
      --***********************************************************************
      -- SINGLE_ENDED input clock input buffers
      --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
-        port map (
-          I  => sys_clk,
-          O  => sys_clk_ibufg
-          );
+      --u_ibufg_sys_clk : IBUFG
+      --  port map (
+      --    I  => sys_clk,
+      --    O  => sys_clk_ibufg
+      --    );
+    sys_clk_ibufg <= sys_clk;
  end generate;   

  --***************************************************************************

--- a/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd
+++ b/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd
@@ -165,11 +165,12 @@ begin
      --***********************************************************************
      -- SINGLE_ENDED input clock input buffers
      --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
-        port map (
-          I  => sys_clk,
-          O  => sys_clk_ibufg
-          );
+      --u_ibufg_sys_clk : IBUFG
+      --  port map (
+      --    I  => sys_clk,
+      --    O  => sys_clk_ibufg
+      --    );
+    sys_clk_ibufg <= sys_clk;
  end generate;   

  --***************************************************************************

--- a/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/memc5_infrastructure.vhd
+++ b/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/memc5_infrastructure.vhd
@@ -165,11 +165,12 @@ begin
      --***********************************************************************
      -- SINGLE_ENDED input clock input buffers
      --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
-        port map (
-          I  => sys_clk,
-          O  => sys_clk_ibufg
-          );
+      --u_ibufg_sys_clk : IBUFG
+      --  port map (
+      --    I  => sys_clk,
+      --    O  => sys_clk_ibufg
+      --    );
+    sys_clk_ibufg <= sys_clk;
  end generate;   

  --***************************************************************************

--- a/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd
+++ b/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd
@@ -165,11 +165,12 @@ begin
      --***********************************************************************
      -- SINGLE_ENDED input clock input buffers
      --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
-        port map (
-          I  => sys_clk,
-          O  => sys_clk_ibufg
-          );
+      --u_ibufg_sys_clk : IBUFG
+      --  port map (
+      --    I  => sys_clk,
+      --    O  => sys_clk_ibufg
+      --    );
+    sys_clk_ibufg <= sys_clk;
  end generate;   

  --***************************************************************************

--- a/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/memc1_infrastructure.vhd
+++ b/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/memc1_infrastructure.vhd
@@ -165,11 +165,12 @@ begin
      --***********************************************************************
      -- SINGLE_ENDED input clock input buffers
      --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
-        port map (
-          I  => sys_clk,
-          O  => sys_clk_ibufg
-          );
+      --u_ibufg_sys_clk : IBUFG
+      --  port map (
+      --    I  => sys_clk,
+      --    O  => sys_clk_ibufg
+      --    );
+    sys_clk_ibufg <= sys_clk;
  end generate;   

  --***************************************************************************

--- a/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_infrastructure.vhd
+++ b/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_infrastructure.vhd
@@ -165,11 +165,12 @@ begin
      --***********************************************************************
      -- SINGLE_ENDED input clock input buffers
      --***********************************************************************
-      u_ibufg_sys_clk : IBUFG
-        port map (
-          I  => sys_clk,
-          O  => sys_clk_ibufg
-          );
+      --u_ibufg_sys_clk : IBUFG
+      --  port map (
+      --    I  => sys_clk,
+      --    O  => sys_clk_ibufg
+      --    );
+    sys_clk_ibufg <= sys_clk;
  end generate;   

  --***************************************************************************