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DDR3 controller for Spartan6
Commit 33b31655 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: minor code cleanup

parent f2c4142a
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Showing with 5 additions and 167 deletions
hdl/rtl/ddr3_ctrl.vhd
View file @ 33b31655
......@@ -269,146 +269,6 @@ end entity ddr3_ctrl;
--==============================================================================
architecture rtl of ddr3_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component ddr3_ctrl_wb
generic(
g_BYTE_ADDR_WIDTH : integer := 30;
g_MASK_SIZE : integer := 4;
g_DATA_PORT_SIZE : integer := 32
);
port(
rst_n_i : in std_logic;
ddr_cmd_clk_o : out std_logic;
ddr_cmd_en_o : out std_logic;
ddr_cmd_instr_o : out std_logic_vector(2 downto 0);
ddr_cmd_bl_o : out std_logic_vector(5 downto 0);
ddr_cmd_byte_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
ddr_cmd_empty_i : in std_logic;
ddr_cmd_full_i : in std_logic;
ddr_wr_clk_o : out std_logic;
ddr_wr_en_o : out std_logic;
ddr_wr_mask_o : out std_logic_vector(g_MASK_SIZE - 1 downto 0);
ddr_wr_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
ddr_wr_full_i : in std_logic;
ddr_wr_empty_i : in std_logic;
ddr_wr_count_i : in std_logic_vector(6 downto 0);
ddr_wr_underrun_i : in std_logic;
ddr_wr_error_i : in std_logic;
ddr_rd_clk_o : out std_logic;
ddr_rd_en_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
ddr_rd_full_i : in std_logic;
ddr_rd_empty_i : in std_logic;
ddr_rd_count_i : in std_logic_vector(6 downto 0);
ddr_rd_overflow_i : in std_logic;
ddr_rd_error_i : in std_logic;
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(31 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic
);
end component ddr3_ctrl_wb;
component ddr3_ctrl_wrapper
generic(
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
g_MEMCLK_PERIOD : integer := 3000;
g_CALIB_SOFT_IP : string := "TRUE";
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
g_SIMULATION : string := "FALSE";
g_NUM_DQ_PINS : integer := 16;
g_MEM_ADDR_WIDTH : integer := 14;
g_MEM_BANKADDR_WIDTH : integer := 3;
g_P0_MASK_SIZE : integer := 4;
g_P0_DATA_PORT_SIZE : integer := 32;
g_P0_BYTE_ADDR_WIDTH : integer := 30;
g_P1_MASK_SIZE : integer := 4;
g_P1_DATA_PORT_SIZE : integer := 32;
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
calib_done_o : out std_logic;
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_odt_o : out std_logic;
ddr3_rst_n_o : out std_logic;
ddr3_cke_o : out std_logic;
ddr3_dm_o : out std_logic;
ddr3_udm_o : out std_logic;
ddr3_dqs_p_b : inout std_logic;
ddr3_dqs_n_b : inout std_logic;
ddr3_udqs_p_b : inout std_logic;
ddr3_udqs_n_b : inout std_logic;
ddr3_clk_p_o : out std_logic;
ddr3_clk_n_o : out std_logic;
ddr3_rzq_b : inout std_logic;
ddr3_zio_b : inout std_logic;
p0_cmd_clk_i : in std_logic;
p0_cmd_en_i : in std_logic;
p0_cmd_instr_i : in std_logic_vector(2 downto 0);
p0_cmd_bl_i : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr_i : in std_logic_vector(g_P0_BYTE_ADDR_WIDTH - 1 downto 0);
p0_cmd_empty_o : out std_logic;
p0_cmd_full_o : out std_logic;
p0_wr_clk_i : in std_logic;
p0_wr_en_i : in std_logic;
p0_wr_mask_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
p0_wr_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full_o : out std_logic;
p0_wr_empty_o : out std_logic;
p0_wr_count_o : out std_logic_vector(6 downto 0);
p0_wr_underrun_o : out std_logic;
p0_wr_error_o : out std_logic;
p0_rd_clk_i : in std_logic;
p0_rd_en_i : in std_logic;
p0_rd_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full_o : out std_logic;
p0_rd_empty_o : out std_logic;
p0_rd_count_o : out std_logic_vector(6 downto 0);
p0_rd_overflow_o : out std_logic;
p0_rd_error_o : out std_logic;
p1_cmd_clk_i : in std_logic;
p1_cmd_en_i : in std_logic;
p1_cmd_instr_i : in std_logic_vector(2 downto 0);
p1_cmd_bl_i : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr_i : in std_logic_vector(g_P1_BYTE_ADDR_WIDTH - 1 downto 0);
p1_cmd_empty_o : out std_logic;
p1_cmd_full_o : out std_logic;
p1_wr_clk_i : in std_logic;
p1_wr_en_i : in std_logic;
p1_wr_mask_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
p1_wr_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full_o : out std_logic;
p1_wr_empty_o : out std_logic;
p1_wr_count_o : out std_logic_vector(6 downto 0);
p1_wr_underrun_o : out std_logic;
p1_wr_error_o : out std_logic;
p1_rd_clk_i : in std_logic;
p1_rd_en_i : in std_logic;
p1_rd_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full_o : out std_logic;
p1_rd_empty_o : out std_logic;
p1_rd_count_o : out std_logic_vector(6 downto 0);
p1_rd_overflow_o : out std_logic;
p1_rd_error_o : out std_logic
);
end component ddr3_ctrl_wrapper;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
......@@ -471,7 +331,7 @@ begin
------------------------------------------------------------------------------
-- PORT 0
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wb_0 : ddr3_ctrl_wb
cmp_ddr3_ctrl_wb_0 : entity work.ddr3_ctrl_wb
generic map(
g_BYTE_ADDR_WIDTH => g_P0_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P0_MASK_SIZE,
......@@ -518,7 +378,7 @@ begin
------------------------------------------------------------------------------
-- PORT 1
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wb_1 : ddr3_ctrl_wb
cmp_ddr3_ctrl_wb_1 : entity work.ddr3_ctrl_wb
generic map(
g_BYTE_ADDR_WIDTH => g_P1_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_P1_MASK_SIZE,
......@@ -565,7 +425,7 @@ begin
------------------------------------------------------------------------------
-- DDR controller wrapper
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wrapper : ddr3_ctrl_wrapper
cmp_ddr3_ctrl_wrapper : entity work.ddr3_ctrl_wrapper
generic map(
g_RST_ACT_LOW => g_RST_ACT_LOW,
g_BANK_PORT_SELECT => g_BANK_PORT_SELECT,
......
hdl/rtl/ddr3_ctrl_pkg.vhd
View file @ 33b31655
......@@ -60,11 +60,6 @@ use IEEE.NUMERIC_STD.all;
--==============================================================================
package ddr3_ctrl_pkg is
--==============================================================================
--! Functions declaration
--==============================================================================
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
--==============================================================================
......@@ -262,21 +257,3 @@ package ddr3_ctrl_pkg is
end ddr3_ctrl_pkg;
package body ddr3_ctrl_pkg is
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end ddr3_ctrl_pkg;
hdl/rtl/ddr3_ctrl_wb.vhd
View file @ 33b31655
......@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-07-13
-- Last update: 2016-05-19
-- Last update: 2018-11-12
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Wishbone interface for DDR3 controller.
......@@ -55,6 +55,7 @@ use IEEE.NUMERIC_STD.all;
--! Specific packages
library work;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
--==============================================================================
--! Entity declaration for ddr3_ctrl_wb
......
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