Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
D
DDR3 controller for Spartan6
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
DDR3 controller for Spartan6
Repository
8de0e83edfbe5e75a187293ea763f0a3770ba7f8
Switch branch/tag
ddr3-sp6-core
hdl
rtl
ddr3_ctrl_wb.vhd
Find file
Blame
History
Permalink
hdl: Fix wishbone interface. Now ignores stb if cyc is '0'.
· 8de0e83e
Matthieu Cattin
authored
Jul 19, 2013
8de0e83e
ddr3_ctrl_wb.vhd
12.9 KB
Edit
Web IDE
Replace ddr3_ctrl_wb.vhd
×
Attach a file by drag & drop or
click to upload
Commit message
Replace ddr3_ctrl_wb.vhd
Replace file
Cancel
A new branch will be created in your fork and a new merge request will be started.
