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AsyncArt
Commit 5d6d2643 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Provide micropipeline length as parameter in the iCEstick demo

parent 22b98a70
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Showing with 15 additions and 14 deletions
demo/hardware/micropipeline.v
View file @ 5d6d2643
...@@ -24,8 +24,6 @@ module top( ...@@ -24,8 +24,6 @@ module top(
wire is_transmitting; wire is_transmitting;
wire recv_error; wire recv_error;
parameter PIPE_DEPTH = 3;
wire [31:0] data_micropipeline; wire [31:0] data_micropipeline;
reg act, rst; reg act, rst;
...@@ -56,7 +54,10 @@ module top( ...@@ -56,7 +54,10 @@ module top(
end end
asyncart_demo asyncart_demo_instance ( asyncart_demo #(
.micropipeline_depth(4)
)
asyncart_demo_instance (
.act_in(act), .act_in(act),
.rst_in(rst), .rst_in(rst),
.data_out(data_micropipeline) .data_out(data_micropipeline)
......
hdl/verilog/asyncart_demo.v
View file @ 5d6d2643
...@@ -30,11 +30,11 @@ module asyncart_demo( ...@@ -30,11 +30,11 @@ module asyncart_demo(
wire reset = 0; wire reset = 0;
wire enable = 1; wire enable = 1;
parameter PIPE_DEPTH = 3; parameter micropipeline_depth = 3;
wire [PIPE_DEPTH-1:0] fire; wire [micropipeline_depth-1:0] fire;
wire [PIPE_DEPTH-1:0] phase; wire [micropipeline_depth-1:0] phase;
wire [31:0] data_link [PIPE_DEPTH:0]; wire [31:0] data_link [micropipeline_depth:0];
wire act, rst; wire act, rst;
assign act = act_in; assign act = act_in;
...@@ -52,7 +52,7 @@ module asyncart_demo( ...@@ -52,7 +52,7 @@ module asyncart_demo(
genvar i; genvar i;
generate generate
for (i=1; i<PIPE_DEPTH-1; i=i+1) begin : asyncart_reg_block for (i=1; i<micropipeline_depth-1; i=i+1) begin : asyncart_reg_block
asyncart_reg asyncart_reg_instance ( asyncart_reg asyncart_reg_instance (
.fire_out(fire[i]), .fire_out(fire[i]),
.phase_out(phase[i]), .phase_out(phase[i]),
...@@ -66,9 +66,9 @@ module asyncart_demo( ...@@ -66,9 +66,9 @@ module asyncart_demo(
asyncart_sink asyncart_sink_instance ( asyncart_sink asyncart_sink_instance (
.fire_out(fire[PIPE_DEPTH-1]), .fire_out(fire[micropipeline_depth-1]),
.phase_out(phase[PIPE_DEPTH-1]), .phase_out(phase[micropipeline_depth-1]),
.phase_in_pos(phase[PIPE_DEPTH-2]), .phase_in_pos(phase[micropipeline_depth-2]),
.act(act), .act(act),
.rst(rst) .rst(rst)
); );
...@@ -77,7 +77,7 @@ module asyncart_demo( ...@@ -77,7 +77,7 @@ module asyncart_demo(
genvar j; genvar j;
generate generate
for (j=0; j<=PIPE_DEPTH-1; j=j+1) begin : sync_register_block for (j=0; j<=micropipeline_depth-1; j=j+1) begin : sync_register_block
sync_register_32b sync_register_32b_instance ( sync_register_32b sync_register_32b_instance (
.data_in(data_link[j]), .data_in(data_link[j]),
.data_out(data_link[j+1]), .data_out(data_link[j+1]),
...@@ -92,7 +92,7 @@ module asyncart_demo( ...@@ -92,7 +92,7 @@ module asyncart_demo(
// Implement an Up-Counter in the source register (first pipeline stage) // Implement an Up-Counter in the source register (first pipeline stage)
assign data_link[0] = data_link[1] + 1; assign data_link[0] = data_link[1] + 1;
// Connect the Red LEDs to the 4 MSB bits in the sink registed (last pipeline stage) // Connect to the output the contents of the sink register (last pipeline stage)
assign data_out = data_link[PIPE_DEPTH]; assign data_out = data_link[micropipeline_depth];
endmodule endmodule
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