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All issues for this milestone are closed. You may close the milestone now.
Project | Open issues | State | Due date |
---|---|---|---|
wr2rf-vme | 0 | Open |
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
12
- wr2rf-vme · trigger regulators
- wr2rf-vme · P1V0 plane
- wr2rf-vme · More GND stitching vias around criticial signal vias
- wr2rf-vme · Delay matching of RF_CH2.MAIN.IQDAC data lines
- wr2rf-vme · Increase distance between J1 and SFP
- wr2rf-vme · Remove soldermask from ESD strip
- wr2rf-vme · With just one pair of vias, connect the fast caps first, not the big ones
- wr2rf-vme · Consider adding ground guard traces to the OCXO clock and the GTX lines
- wr2rf-vme · Plane resonance at low frequencies (around 300MHz)
- wr2rf-vme · Net NetC304_2 (for IC86's feedback) passes right over LVDS signals
- wr2rf-vme · Fix FPGA pin assignment
- wr2rf-vme · DRC rules incomplete for vias under pads.