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Fix to CDC constraints generator matching filters
general-cores!43
· opened
Aug 17, 2023
by
André Pinho
MERGED
1
8
updated
Mar 13, 2024
[fix][testsuite][vivado] Adjust Testsuite to !14
hdl-make!15
· opened
Mar 10, 2022
by
Istvan Kiss
develop
MERGED
1
1
updated
Mar 10, 2022
WIP: Pieter fasec wrpc v5
wr-cores!14
· opened
May 10, 2024
by
Pieter Van Trappen
0
updated
May 10, 2024
tools/genrammem: Create wrc.mem file to use with Vivado's `updatemem` command
wrpc-sw!19
· opened
May 03, 2024
by
Frederik Pfautsch
0
updated
May 03, 2024
gc argb led drv
general-cores!67
· opened
May 03, 2024
by
Tristan Gingold
MERGED
0
updated
May 03, 2024
Add macro-based dpram for Xilinx/AMD 7Series FPGA
general-cores!66
· opened
May 02, 2024
by
Frederik Pfautsch
MERGED
0
updated
May 03, 2024
dev/simple-uart.c: Implement missing purge functions
wrpc-sw!18
· opened
May 02, 2024
by
Frederik Pfautsch
0
updated
May 02, 2024
modules/wrc_core/wrc_periph: I2C HIGH init value
wr-cores!13
· opened
May 02, 2024
by
Frederik Pfautsch
0
updated
May 02, 2024
Addition of board specific OID that we need to control the timing output of the…
wrpc-sw!17
· opened
Apr 29, 2024
by
Konstantinos Asteriou
wrpc-v5
MERGED
0
updated
May 15, 2024
add -min argument to get_property PERIOD to return the minimum value of the returned list
general-cores!65
· opened
Apr 16, 2024
by
Julien Egli
MERGED
0
updated
Apr 16, 2024
fix snmp sfp dom accuracy
wr-switch-sw!5
· opened
Mar 19, 2024
by
Fabian Mauchle
bug
0
updated
Mar 19, 2024
preserve dot-config during firmware upgrade
wr-switch-sw!4
· opened
Mar 12, 2024
by
Fabian Mauchle
0
updated
Mar 12, 2024
WIP: Resolve "Use Verible for Verilog formatting"
urv-core!4
· opened
Feb 12, 2024
by
Shareef Jalloq
0
updated
Feb 12, 2024
WIP: Resolve "Bug: register x0 should be hardwired to zero"
urv-core!3
· opened
Feb 12, 2024
by
Shareef Jalloq
0
updated
Feb 12, 2024
Resolve "Would you be happy to integrate FuseSoC core files into the repo?"
urv-core!2
· opened
Feb 07, 2024
by
Shareef Jalloq
MERGED
1
updated
Feb 12, 2024
Resolve "Support Verilog output with gen_sourceid tool"
general-cores!63
· opened
Jan 30, 2024
by
Dimitris Lampridis
MERGED
1
updated
Jan 30, 2024
Option to include .mk at end of generated Makefile
hdl-make!30
· opened
Jan 25, 2024
by
Istvan Kiss
develop
0
updated
Jan 25, 2024
Add support for legacy LiberoSoC 11.9 as separate tool file, ProASIC3 support; rebased onto latest Develop branch
hdl-make!29
· opened
Jan 24, 2024
by
Istvan Kiss
develop
6
updated
Jan 25, 2024
Resolve "Linux driver for wb simple uart"
general-cores!62
· opened
Jan 24, 2024
by
Konstantinos Blantos
software
MERGED
0
updated
Mar 11, 2024
Resolve "possible_fix_in_wb_uart_rx_fifo"
general-cores!61
· opened
Jan 23, 2024
by
Konstantinos Blantos
CLOSED
0
updated
Jan 26, 2024
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