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wr-switch-sw
Commit 4ede2a74 authored by Alessandro Rubini's avatar Alessandro Rubini
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userspace/libswitchhw: removed trailing blanks

parent f3182b48
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Showing with 126 additions and 126 deletions
userspace/libswitchhw/ad9516.c
View file @ 4ede2a74
......@@ -219,7 +219,7 @@ int shw_ad9516_init()
// ad9516_power_down();
shw_udelay(10000);
if(ad9516_read_reg(AD9516_SERIALPORT) != 0x18)
......@@ -234,7 +234,7 @@ int shw_ad9516_init()
} else {
assert_init(ad9516_load_state(&ad9516_regs_tcxo_25m));
}
// wait for the PLL to lock
while(retries--)
{
......@@ -244,8 +244,8 @@ int shw_ad9516_init()
shw_ad9516_set_output_delay(9, 0.5, 0);
// TRACE(TRACE_INFO, "LockReg: %d\n",
// TRACE(TRACE_INFO, "LockReg: %d\n",
return 0;
}
......@@ -253,8 +253,8 @@ static int find_optimal_params(float delay_ns, int *caps, int *frac, int *ramp,
{
int r, i, ncaps, f;
float best_error = 10000;
for(r = 0; r < 8; r++)
{
for(i=0;i<8;i++)
......@@ -269,10 +269,10 @@ static int find_optimal_params(float delay_ns, int *caps, int *frac, int *ramp,
float iramp = (float)(r+1)*200.0;
float del_range = 200.0 * ((float)(ncaps+3)/iramp) * 1.3286;
float offset = 0.34 + (1600.0 - iramp) * 10e-4 + (float)(ncaps-1)/iramp*6.0;
// printf("range: %.3f offset %.3f\n", del_range, offset);
float del_fine = del_range * (float)f / 63.0 + offset;
if(fabs(del_fine - delay_ns) < best_error)
if(fabs(del_fine - delay_ns) < best_error)
{
// printf("New Best: %.3f\n", del_fine);
best_error = fabs(del_fine - delay_ns);
......@@ -291,12 +291,12 @@ int shw_ad9516_set_output_delay(int output, float delay_ns, int bypass)
uint16_t regbase = 0xa0 + 3*(output - 6);
int ramp,frac,caps;
float best_dly;
find_optimal_params(delay_ns,&caps, &frac, &ramp, &best_dly );
// printf("Opt: caps %d frac %d ramp %d best %.5f req %.5f regbase %x\n", caps, frac, ramp, best_dly, delay_ns, regbase);
ad9516_write_reg(regbase, bypass?1:0);
ad9516_write_reg(regbase+1, (caps << 3) | (ramp));
......
userspace/libswitchhw/ad9516_default_regs.h
View file @ 4ede2a74
......@@ -14,7 +14,7 @@ static const struct ad9516_regs ad9516_regs_tcxo_25m = {
{ 0x0011, 5}, // R div
{ 0x0012, 0x00},
{ 0x0013, 12},// A div
{ 0x0014, 18},// B div -- vco =
{ 0x0014, 18},// B div -- vco =
{ 0x0015, 0x00},
{ 0x0016, 5}, // 16/17 mode
{ 0x0017, 0x00},
......
userspace/libswitchhw/clkb_io.c
View file @ 4ede2a74
......@@ -72,7 +72,7 @@ int shw_clkb_init_cmi()
int shw_clkb_init()
{
shw_pio_configure(PIN_clkb_fpga_nrst);
shw_pio_set0(PIN_clkb_fpga_nrst);
......
userspace/libswitchhw/dmpll.c
View file @ 4ede2a74
......@@ -58,14 +58,14 @@ static void dmpll_set_phase_shift(int channel, int ps_shift)
switch(channel)
{
case DMPLL_CHANNEL_UP0:
case DMPLL_CHANNEL_UP0:
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN0, ps_shift);
break;
case DMPLL_CHANNEL_UP1:
case DMPLL_CHANNEL_UP1:
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN1, ps_shift);
break;
}
}
......@@ -79,7 +79,7 @@ int shw_dmpll_check_lock()
return 0;
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSR, DMPLL_PSR_LOCK_LOST); // clear loss-of-lock bit
}
// printf("DPSR %x\n",psr & (DMPLL_PSR_FREQ_LK | DMPLL_PSR_PHASE_LK));
return (psr & DMPLL_PSR_FREQ_LK);// && (psr & DMPLL_PSR_PHASE_LK);
}
......@@ -88,14 +88,14 @@ static int dmpll_shifter_busy(int channel)
{
switch(channel)
{
case DMPLL_CHANNEL_UP0:
case DMPLL_CHANNEL_UP0:
return shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN0) & DMPLL_PSCR_IN0_BUSY;
case DMPLL_CHANNEL_UP1:
case DMPLL_CHANNEL_UP1:
return shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN1) & DMPLL_PSCR_IN1_BUSY;
}
return 0;
return 0;
}
\
......@@ -106,19 +106,19 @@ static int iface_to_channel(const char *source)
return DMPLL_CHANNEL_UP0;
else if(!strcmp(source,"wru1"))
return DMPLL_CHANNEL_UP1;
return -1;
}
}
int shw_dmpll_lock(const char *source)
{
int ref_clk = iface_to_channel(source);
if(ref_clk < 0) {
TRACE(TRACE_ERROR, "Unknown clock source...");
return -1;
}
TRACE(TRACE_INFO,"DMPLL: Set refence input to: %s", source);
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PCR, 0);
......@@ -128,9 +128,9 @@ int shw_dmpll_lock(const char *source)
dmpll_set_deglitch_threshold(DMPLL_REG_DGCR_FB, cur_state.deglitch_threshold);
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN0, 0);
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN1, 0);
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN2, 0);
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN2, 0);
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN3, 0);
// gains & thresholds
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_FBGR, DMPLL_FBGR_F_KP_W(-100) | DMPLL_FBGR_F_KI_W(-600));
......@@ -155,9 +155,9 @@ int shw_dmpll_phase_shift(const char *source, int phase_shift)
// TRACE(TRACE_INFO,"shw_DMPLL_phase_shift source %s ref %d ps %d\n", source, ref_clk, phase_shift);
if(ref_clk < 0) return -1;
ps = (double)phase_shift / 8000.0 * (double) shw_hpll_get_divider();
dmpll_set_phase_shift(ref_clk, (int) ps);
return 0;
}
......
userspace/libswitchhw/fpgaboot.c
View file @ 4ede2a74
......@@ -41,7 +41,7 @@ static int get_fpga_revid(int fpga_id, uint32_t *fw_hash, uint32_t *rev_id)
{
// check the magic register value
if(_fpga_readl(FPGA_BASE_REVID + REVID_REG_MAGIC) != REVID_MAGIC_VALUE) return -1;
*fw_hash = _fpga_readl(FPGA_BASE_REVID + REVID_REG_FW_HASH);
*rev_id = _fpga_readl(FPGA_BASE_REVID + REVID_REG_FW_REVISION);
return 0;
......@@ -69,16 +69,16 @@ static char * read_string(FILE *f)
{
char buf[1024];
uint32_t len;
if(read_le32(f, &len) < 0)
return NULL;
if(len > sizeof(buf)-1)
return NULL;
fread(buf, 1, len, f);
buf[len]=0;
return strdup(buf);
}
......@@ -86,13 +86,13 @@ static int read_image_header(FILE *f, struct fpga_image_entry *ent)
{
struct fpga_image_header hdr;
int rc = 0;
if( fread(&hdr, sizeof(struct fpga_image_header), 1, f) != 1)
return -1;
if(memcmp(hdr.magic, FPGA_IMAGE_MAGIC, 4))
return -1;
ent->fpga_name = read_string(f);
ent->fw_name = read_string(f);
rc = read_le32(f, &ent->hash_reg);
......@@ -101,7 +101,7 @@ static int read_image_header(FILE *f, struct fpga_image_entry *ent)
rc |= read_le32(f, &ent->compressed_size);
if(!ent->fpga_name || !ent->fw_name || rc) return -1;
return 0;
}
......@@ -129,11 +129,11 @@ static int find_fpga_image(int fpga_id, const char *fw_name, int rev_id, uint32_
FILE *f;
struct dirent **namelist;
int n;
char latest_image_name[1024];
int found = 0;
int max_rev = -1;
n = scandir(fpga_image_dir, &namelist, 0, alphasort);
if(n<0)
......@@ -141,22 +141,22 @@ static int find_fpga_image(int fpga_id, const char *fw_name, int rev_id, uint32_
TRACE(TRACE_FATAL, "Scanning the FPGA image directory (%s) failed.", fpga_image_dir);
return -1;
}
while(n--)
{
char namebuf[1024];
strncpy(namebuf, fpga_image_dir, 1024);
strncat(namebuf, "/", 1024);
strncat(namebuf, namelist[n]->d_name, 1024);
if(!stat_is_file(namebuf)) continue;
f = fopen(namebuf, "rb");
if(f)
{
struct fpga_image_entry ent;
if(!read_image_header(f, &ent))
if(!read_image_header(f, &ent))
{
TRACE(TRACE_INFO,"CheckFW: %s [%s] rev %d", ent.fpga_name, ent.fw_name, ent.revision);
if(rev_id) // name-based lookup
......@@ -165,7 +165,7 @@ static int find_fpga_image(int fpga_id, const char *fw_name, int rev_id, uint32_
&& !strcasecmp(ent.fw_name, fw_name))
{
found = 1;
if((int)ent.revision > max_rev)
{
max_rev = ent.revision;
......@@ -173,7 +173,7 @@ static int find_fpga_image(int fpga_id, const char *fw_name, int rev_id, uint32_
}
}
} else { // revid-based lookup: we look for newer firmware with matching revid
if(ent.hash_reg == fw_hash && (int)ent.revision > max_rev)
{
found = 1;
......@@ -192,10 +192,10 @@ static int find_fpga_image(int fpga_id, const char *fw_name, int rev_id, uint32_
if(!found)
return -1;
if(rev_id >= 0 && max_rev <= rev_id)
return -1;
f = fopen(latest_image_name, "rb");
read_image_header(f, ent_h);
......@@ -203,7 +203,7 @@ static int find_fpga_image(int fpga_id, const char *fw_name, int rev_id, uint32_
ent_h -> image_buf = shw_malloc(ent_h->compressed_size);
fread(ent_h->image_buf, 1, ent_h->compressed_size, f);
fclose(f);
fclose(f);
return 0;
}
......@@ -229,10 +229,10 @@ static int uncompress_and_boot_fpga(int fpga_id, struct fpga_image_entry *ent)
int rc = shw_load_fpga_bitstream(fpga_id, bitstream, ent->size);
shw_free(bitstream);
shw_free(ent->image_buf);
return rc;
}
......@@ -252,10 +252,10 @@ int shw_boot_fpga(int fpga_id)
fpga_name = expand_fpga_id(fpga_id);
TRACE(TRACE_INFO, "%s: reading REV_ID...", fpga_name);
if(get_fpga_revid (fpga_id, &fw_hash, (uint32_t *)&rev_id) < 0)
rev_id = -1;
switch(fpga_id)
{
case FPGA_ID_MAIN:
......@@ -263,7 +263,7 @@ int shw_boot_fpga(int fpga_id)
case FPGA_ID_CLKB:
fw_name = firmware_clkb; break;
}
if(rev_id < 0 || force_new_firmware)
{
TRACE(TRACE_INFO, "%s: invalid REV_ID or forced firmware update. Trying to boot the FPGA with the firmware: %s", fpga_name, fw_name)
......@@ -273,19 +273,19 @@ int shw_boot_fpga(int fpga_id)
shw_exit_fatal();
return -1;
}
return uncompress_and_boot_fpga(fpga_id, &ent);
} else {
TRACE(TRACE_INFO, "%s: got REV_ID (rev = %d, hash = %x). Looking for newer firmware", fpga_name, rev_id, fw_hash);
rc = find_fpga_image(fpga_id, fw_name, rev_id, fw_hash, &ent);
if(rc < 0) {
TRACE(TRACE_INFO, "%s: no more recent image found", fpga_name);
return 0;
} else return uncompress_and_boot_fpga(fpga_id, &ent);
}
return -1;
}
......
userspace/libswitchhw/hpll.c
View file @ 4ede2a74
......@@ -46,7 +46,7 @@ static inline void hpll_write(uint32_t reg, uint32_t value)
/* static void hpll_poll_rfifo() */
/* { */
/* while(1) */
/* { */
/* if((hpll_read(HPLL_REG_RFIFO_CSR) & HPLL_RFIFO_CSR_EMPTY) || rfifo_nmeas >= MAX_MEAS) return; */
......@@ -66,23 +66,23 @@ void shw_hpll_ramp_gain(double kp_new, double ki_new)
{
uint64_t init_tics = shw_get_tics();
int step = 0;
cur_params.kp_phase = kp_new;
cur_params.ki_phase = ki_new;
for(step = 0; step < cur_params.phase_gain_steps; step++)
{
// if(shw_get_tics() - init_tics > (uint64_step * cur_params.phase_gain_step_delay)
{
double kp, ki;
kp = interpolate(cur_params.kp_phase_cur,cur_params.kp_phase, step, cur_params.phase_gain_steps);
ki = interpolate(cur_params.ki_phase_cur,cur_params.ki_phase, step, cur_params.phase_gain_steps);
// TRACE(TRACE_INFO, "ramping down the HPLL gain (Kp = %.5f Ki = %.5f)", kp, ki);
hpll_write(HPLL_REG_PBGR,
hpll_write(HPLL_REG_PBGR,
HPLL_PBGR_P_KP_W(FLOAT_TO_FB_COEF(kp)) |
HPLL_PBGR_P_KI_W(FLOAT_TO_FB_COEF(ki)));
// } else {
......@@ -106,10 +106,10 @@ void shw_hpll_load_regs(const hpll_params_t *params)
hpll_write(HPLL_REG_DIVR, // select the division ratio
HPLL_DIVR_DIV_FB_W(params->N + params->delta) |
HPLL_DIVR_DIV_REF_W(params->N));
TRACE(TRACE_INFO,"DIV_REF = %d, DIV_FB = %d", params->N, params->N + params->delta);
hpll_write(HPLL_REG_FBGR, // set frequency detector gain
HPLL_FBGR_F_KP_W(FLOAT_TO_FB_COEF(params->kp_freq)) |
HPLL_FBGR_F_KI_W(FLOAT_TO_FB_COEF(params->ki_freq)));
......@@ -143,10 +143,10 @@ void shw_hpll_load_regs(const hpll_params_t *params)
TRACE(TRACE_INFO,"TargetFreqErr = %d, FreqGating = %d PhaseGating = %d", target_freq_err, params->freq_gating, params->phase_gating);
// enable the PLL, set DAC clock, reference clock, etc.
hpll_write(HPLL_REG_PCR,
hpll_write(HPLL_REG_PCR,
// HPLL_PCR_FORCE_F |
HPLL_PCR_ENABLE | // enable the PLL
HPLL_PCR_SWRST | // force software reset
......@@ -157,14 +157,14 @@ void shw_hpll_load_regs(const hpll_params_t *params)
// init_tics = shw_get_tics();
memcpy(&cur_params, params, sizeof(hpll_params_t));
cur_params.kp_phase_cur = params->kp_phase;
cur_params.ki_phase_cur = params->ki_phase;
// shw_hpll_ramp_gain(0.1, 0.00384);
shw_hpll_ramp_gain(0.0384, 0.00384);
}
......@@ -190,15 +190,15 @@ int shw_hpll_check_lock()
uint32_t psr;
psr= hpll_read(HPLL_REG_PSR);
if(psr & HPLL_PSR_LOCK_LOST) {
return 0;
hpll_write(HPLL_REG_PSR, HPLL_PSR_LOCK_LOST); // clear loss-of-lock bit
}
printf("PSR %x\n",psr & (HPLL_PSR_FREQ_LK | HPLL_PSR_PHASE_LK));
printf("PCR %x\n", hpll_read(HPLL_REG_PCR));
//
// return 1;
return (psr & HPLL_PSR_FREQ_LK) && (psr & HPLL_PSR_PHASE_LK);
......@@ -225,9 +225,9 @@ int shw_hpll_switch_reference(const char *if_name)
{
hpll_params_t my_params;
TRACE(TRACE_INFO, "HPLL: Set reference input to: %s", if_name);
memcpy(&my_params, &default_hpll_params, sizeof(hpll_params_t));
if(!strcmp(if_name, "wru0"))
my_params.ref_sel = HPLL_REFSEL_UP0_RBCLK;
else if(!strcmp(if_name, "wru1"))
......@@ -236,6 +236,6 @@ int shw_hpll_switch_reference(const char *if_name)
my_params.ref_sel = HPLL_REFSEL_LOCAL;
else
TRACE(TRACE_FATAL, "unrecognized HPLL reference clock: %s", if_name);
shw_hpll_load_regs(&my_params);
}
userspace/libswitchhw/phy_calibration.c
View file @ 4ede2a74
......@@ -65,7 +65,7 @@ static int cal_current_port_type;
static int uplink_calibrator_configure(int n_avg, int lane, int index)
{
int input;
if(lane == PHY_CALIBRATE_TX)
input = UPLINK_CAL_IN_REFCLK;
else if(lane == PHY_CALIBRATE_RX)
......@@ -75,8 +75,8 @@ static int uplink_calibrator_configure(int n_avg, int lane, int index)
else
input = UPLINK_CAL_IN_UP1_RBCLK;
}
shw_clkb_write_reg(CLKB_BASE_CALIBRATOR + DPC_REG_CR, 0);
shw_clkb_write_reg(CLKB_BASE_CALIBRATOR + DPC_REG_CR, DPC_CR_EN | DPC_CR_N_AVG_W(n_avg) | DPC_CR_IN_SEL_W(input));
}
......@@ -86,15 +86,15 @@ int route_order[8] = {0,1,2,3,4,5,6,7};
static int downlink_calibrator_configure(int n_avg, int lane, int index)
{
int input;
if(lane == PHY_CALIBRATE_TX)
input = DOWNLINK_CAL_IN_REFCLK;
else if(lane == PHY_CALIBRATE_RX)
{
input = DOWNLINK_CAL_IN_RBCLK(route_order[index]);
}
_fpga_writel(FPGA_BASE_CALIBRATOR + DPC_REG_CR, 0);
_fpga_writel(FPGA_BASE_CALIBRATOR + DPC_REG_CR, DPC_CR_EN | DPC_CR_N_AVG_W(n_avg) | DPC_CR_IN_SEL_W(input));
}
......@@ -142,13 +142,13 @@ static int decode_port_name(const char *if_name, int *type, int *index)
return -1;
*index = if_name[3] - '0';
if(!strncmp(if_name, "wru", 3))
*type = PORT_UPLINK;
else if(!strncmp(if_name, "wrd", 3))
*type = PORT_DOWNLINK;
else return -1;
return 0;
}
......@@ -159,9 +159,9 @@ static int do_net_ioctl(const char *if_name, int request, void *data)
ifr.ifr_addr.sa_family = AF_PACKET;
strcpy(ifr.ifr_name, if_name);
ifr.ifr_data = data;
int rv = ioctl(cal_socket, request, &ifr);
return rv;
}
......@@ -173,7 +173,7 @@ int shw_cal_init()
// create a raw socket for calibration/DMTD readout
cal_socket = socket(AF_PACKET, SOCK_DGRAM, 0);
if(cal_socket < 0)
if(cal_socket < 0)
return -1;
return xpoint_configure();
......@@ -187,9 +187,9 @@ int shw_cal_enable_pattern(const char *if_name, int enable)
// TRACE(TRACE_INFO,"port %s enable %d", if_name, enable);
if((rval=decode_port_name(if_name, &type, &index)) < 0) return rval;
crq.cmd = enable ? CAL_CMD_TX_ON : CAL_CMD_TX_OFF;
if(type == PORT_UPLINK)
{
if(do_net_ioctl(if_name, PRIV_IOCGCALIBRATE, &crq) < 0)
......@@ -209,28 +209,28 @@ int shw_cal_enable_feedback(const char *if_name, int enable, int lane)
// TRACE(TRACE_INFO,"port %s enable %d lane %d", if_name, enable, lane);
if((rval=decode_port_name(if_name, &type, &index)) < 0) return rval;
// TRACE(TRACE_INFO, "enable_feedback type:%d index:%d\n", type, index);
cal_current_lane = lane;
cal_current_port_index = index;
cal_current_port_type = type;
strcpy(cal_current_if, if_name);
if(type == PORT_UPLINK)
{
if(enable)
{
switch(lane)
{
case PHY_CALIBRATE_TX:
cal_in_progress = 1;
xpoint_cal_feedback(1, index, 0); // enable PHY TX line feedback
// TRACE(TRACE_INFO, "TX index %d", index);
uplink_calibrator_configure(CAL_DMTD_AVERAGING_STEPS, lane, index);
......@@ -240,8 +240,8 @@ int shw_cal_enable_feedback(const char *if_name, int enable, int lane)
cal_in_progress = 1;
xpoint_cal_feedback(1, index, 1); // enable PHY RX line feedback
crq.cmd = CAL_CMD_RX_ON;
if(do_net_ioctl(if_name, PRIV_IOCGCALIBRATE, &crq) < 0)
......@@ -258,14 +258,14 @@ int shw_cal_enable_feedback(const char *if_name, int enable, int lane)
break;
}
} else { // enable == 0
TRACE(TRACE_INFO, "Disabling calibration on port: %s", if_name);
cal_in_progress = 0;
xpoint_cal_feedback(0, 0, 0);
if(lane == PHY_CALIBRATE_TX)
{
crq.cmd = CAL_CMD_TX_OFF;
......@@ -283,49 +283,49 @@ int shw_cal_enable_feedback(const char *if_name, int enable, int lane)
}
}
int shw_cal_measure(uint32_t *phase)
int shw_cal_measure(uint32_t *phase)
{
int phase_raw;
struct wrmch_calibration_req crq;
if(!cal_in_progress)
return -1;
if(cal_current_port_type == PORT_UPLINK)
{
switch(cal_current_lane)
{
case PHY_CALIBRATE_TX:
fprintf(stderr,"CalTxMeasUplink\n");
if(uplink_calibrator_measure(&phase_raw))
{
*phase = (uint32_t) ((double) phase_raw / (double) CAL_DMTD_AVERAGING_STEPS / (double)shw_hpll_get_divider() * 8000.0);
return 1;
} else return 0;
break;
case PHY_CALIBRATE_RX:
crq.cmd = CAL_CMD_RX_CHECK;
if(do_net_ioctl(cal_current_if, PRIV_IOCGCALIBRATE, &crq) < 0) return -1;
if(crq.cal_present && uplink_calibrator_measure(&phase_raw))
{
*phase = (uint32_t) ((double) phase_raw / (double) CAL_DMTD_AVERAGING_STEPS / (double)shw_hpll_get_divider() * 8000.0);
return 1;
} else return 0;
break;
}
} else {
// TRACE(TRACE_ERROR, "Sorry, no downlinks support yet...\n");
return -1;
}
}
int shw_poll_dmtd(const char *if_name, uint32_t *phase_ps)
......@@ -344,7 +344,7 @@ int shw_poll_dmtd(const char *if_name, uint32_t *phase_ps)
if(!phr.ready) // No valid DMTD measurement?
return 0;
// TRACE(TRACE_INFO,"%s: phase %d", if_name, phr.phase);
*phase_ps = (uint32_t) ((double)phr.phase / (double)shw_hpll_get_divider() * 8000.0);
......
userspace/libswitchhw/pps_gen.c
View file @ 4ede2a74
......@@ -13,10 +13,10 @@
int shw_pps_gen_init()
{
uint32_t cr;
cr = PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_WIDTH);
TRACE(TRACE_INFO, "Initializing PPS generator...");
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, cr);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCLO, 1285700840);
......
userspace/libswitchhw/trace.c
View file @ 4ede2a74
......@@ -40,7 +40,7 @@ void trace_printf(const char *fname, int lineno, int level, const char *fmt, ...
fprintf(trace_file, "%-24s ", linestr);
vfprintf(trace_file, fmt, vargs);
fflush(trace_file);
fprintf(trace_file,"\n");
fprintf(trace_file,"\n");
}
if(trace_to_stderr)
......
userspace/libswitchhw/watchdog.c
View file @ 4ede2a74
......@@ -33,7 +33,7 @@ static inline uint8_t spi_txrx(uint8_t x)
rval <<= 1;
if(shw_pio_get(PIN_sdin)) rval |= 1;
shw_udelay(50);
shw_pio_set1(PIN_sck);
shw_pio_set1(PIN_sck);
shw_udelay(50);
x<<=1;
}
......@@ -55,7 +55,7 @@ static void wd_spi_xfer(uint8_t *buf, int size)
#define WD_CMD_SET_LED 1
#define WD_CMD_FEEDBACK 2
void shw_mbl_set_leds(int port, int led, int mode)
{
......@@ -65,7 +65,7 @@ void shw_mbl_set_leds(int port, int led, int mode)
cmd_buf[1] = port;
cmd_buf[2] = led;
cmd_buf[3] = mode;
wd_spi_xfer(cmd_buf, 4);
}
......@@ -78,7 +78,7 @@ void shw_mbl_cal_feedback(int port, int cmd)
cmd_buf[1] = port;
cmd_buf[2] = cmd;
cmd_buf[3] = 0;
wd_spi_xfer(cmd_buf, 4);
}
......
userspace/libswitchhw/xpoint.c
View file @ 4ede2a74
......@@ -146,7 +146,7 @@ static void mi2c_get_byte(unsigned char *data)
static void mi2c_init()
{
shw_clkb_write_reg(CLKB_BASE_GPIO + GPIO_REG_DDR, MASK_SCL_OUT | MASK_SDA_OUT);
M_SCL_OUT(1);
M_SDA_OUT(1);
}
......@@ -229,7 +229,7 @@ int xpoint_configure()
xpoint_route(XPT_SFP1_TX, XPT_UP1_RX);
xpoint_route(XPT_SFP0_TX, XPT_UP0_RX);
return 0;
}
......
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