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white-rabbit
wr-switch-hdl
Commits
e3778758
Commit
e3778758
authored
Nov 19, 2018
by
Grzegorz Daniluk
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extra low latency triggers, basic test/demo
parent
5f6ac509
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3 changed files
with
201 additions
and
18 deletions
+201
-18
Manifest.py
top/bare_top/Manifest.py
+1
-1
ell.vhd
top/bare_top/ell.vhd
+155
-0
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+45
-17
No files found.
top/bare_top/Manifest.py
View file @
e3778758
files
=
[
"scb_top_bare.vhd"
,
"wb_cpu_bridge.vhd"
,
"wrsw_top_pkg.vhd"
,
"scb_top_sim.vhd"
,
"wrs_sdb_pkg.vhd"
,
"synthesis_descriptor.vhd"
];
"synthesis_descriptor.vhd"
,
"ell.vhd"
];
modules
=
{
"local"
:
[
"../../"
]
};
top/bare_top/ell.vhd
0 → 100644
View file @
e3778758
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wrsw_top_pkg
.
all
;
entity
ell
is
generic
(
g_num_ports
:
integer
:
=
18
);
port
(
-- from endpoints
ep_phys_i
:
in
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
ep_phys_o
:
out
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
-- to serdes
serdes_phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
serdes_phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
));
end
ell
;
architecture
behav
of
ell
is
-- K28.0 is our trigger character
constant
c_TRIG_CHAR
:
std_logic_vector
(
7
downto
0
)
:
=
x"1c"
;
-- K28.1 as second word of the trigger
constant
c_TRIG2_CHAR
:
std_logic_vector
(
7
downto
0
)
:
=
x"3c"
;
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
31
downto
0
);
TRIG1
:
in
std_logic_vector
(
31
downto
0
);
TRIG2
:
in
std_logic_vector
(
31
downto
0
);
TRIG3
:
in
std_logic_vector
(
31
downto
0
));
end
component
;
component
chipscope_icon
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
;
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0
:
std_logic_vector
(
31
downto
0
);
signal
TRIG1
:
std_logic_vector
(
31
downto
0
);
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
signal
detected
:
std_logic_vector
(
1
downto
0
);
signal
temp_phys_out
:
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
begin
detected
(
0
)
<=
'1'
when
(
serdes_phys_i
(
0
)
.
rx_k
(
0
)
=
'1'
and
serdes_phys_i
(
0
)
.
rx_data
(
7
downto
0
)
=
c_TRIG_CHAR
)
else
'0'
;
detected
(
1
)
<=
'1'
when
(
serdes_phys_i
(
0
)
.
rx_k
(
1
)
=
'1'
and
serdes_phys_i
(
0
)
.
rx_data
(
15
downto
8
)
=
c_TRIG_CHAR
)
else
'0'
;
GEN_PHYS_WIRES
:
for
I
in
0
to
g_num_ports
-1
generate
ep_phys_o
(
I
)
.
ref_clk
<=
serdes_phys_i
(
I
)
.
ref_clk
;
ep_phys_o
(
I
)
.
rx_clk
<=
serdes_phys_i
(
I
)
.
rx_clk
;
serdes_phys_o
(
I
)
.
rst
<=
ep_phys_i
(
I
)
.
rst
;
serdes_phys_o
(
I
)
.
loopen
<=
ep_phys_i
(
I
)
.
loopen
;
serdes_phys_o
(
I
)
.
enable
<=
ep_phys_i
(
I
)
.
enable
;
serdes_phys_o
(
I
)
.
syncen
<=
ep_phys_i
(
I
)
.
syncen
;
ep_phys_o
(
I
)
.
rdy
<=
serdes_phys_i
(
I
)
.
rdy
;
ep_phys_o
(
I
)
.
rx_data
<=
serdes_phys_i
(
I
)
.
rx_data
;
ep_phys_o
(
I
)
.
rx_k
<=
serdes_phys_i
(
I
)
.
rx_k
;
ep_phys_o
(
I
)
.
rx_enc_err
<=
serdes_phys_i
(
I
)
.
rx_enc_err
;
ep_phys_o
(
I
)
.
rx_bitslide
<=
serdes_phys_i
(
I
)
.
rx_bitslide
;
ep_phys_o
(
I
)
.
tx_disparity
<=
serdes_phys_i
(
I
)
.
tx_disparity
;
ep_phys_o
(
I
)
.
tx_enc_err
<=
serdes_phys_i
(
I
)
.
tx_enc_err
;
--process(serdes_phys_i(I).ref_clk)
--begin
-- if rising_edge(serdes_phys_i(I).ref_clk) then
-- if (ep_phys_i(I).rst = '1') then
-- ep_phys_o(I).tx_disparity <= '0';
-- ep_phys_o(I).tx_enc_err <= '0';
-- else
-- ep_phys_o(I).tx_disparity <= serdes_phys_i(I).tx_disparity;
-- ep_phys_o(I).tx_enc_err <= serdes_phys_i(I).tx_enc_err;
-- end if;
-- end if;
--end process;
end
generate
;
-- for now port 0 only receives triggers, so it will never inject in its own
-- TX path
process
(
serdes_phys_i
(
0
)
.
ref_clk
)
begin
if
rising_edge
(
serdes_phys_i
(
0
)
.
ref_clk
)
then
if
(
ep_phys_i
(
0
)
.
rst
=
'1'
)
then
serdes_phys_o
(
0
)
.
tx_data
<=
(
others
=>
'0'
);
serdes_phys_o
(
0
)
.
tx_k
<=
(
others
=>
'0'
);
else
serdes_phys_o
(
0
)
.
tx_data
<=
ep_phys_i
(
0
)
.
tx_data
;
serdes_phys_o
(
0
)
.
tx_k
<=
ep_phys_i
(
0
)
.
tx_k
;
end
if
;
end
if
;
end
process
;
GEN_INJ
:
for
I
in
1
to
g_num_ports
-1
generate
process
(
serdes_phys_i
(
I
)
.
ref_clk
)
begin
if
rising_edge
(
serdes_phys_i
(
I
)
.
ref_clk
)
then
if
(
ep_phys_i
(
I
)
.
rst
=
'1'
)
then
temp_phys_out
(
I
)
.
tx_data
<=
ep_phys_i
(
I
)
.
tx_data
;
temp_phys_out
(
I
)
.
tx_k
<=
ep_phys_i
(
I
)
.
tx_k
;
else
if
(
detected
/=
"00"
)
then
temp_phys_out
(
I
)
.
tx_data
(
15
downto
8
)
<=
c_TRIG_CHAR
;
temp_phys_out
(
I
)
.
tx_data
(
7
downto
0
)
<=
c_TRIG2_CHAR
;
temp_phys_out
(
I
)
.
tx_k
<=
"11"
;
else
temp_phys_out
(
I
)
.
tx_data
<=
ep_phys_i
(
I
)
.
tx_data
;
temp_phys_out
(
I
)
.
tx_k
<=
ep_phys_i
(
I
)
.
tx_k
;
end
if
;
end
if
;
end
if
;
end
process
;
serdes_phys_o
(
I
)
.
tx_data
<=
temp_phys_out
(
I
)
.
tx_data
;
serdes_phys_o
(
I
)
.
tx_k
<=
temp_phys_out
(
I
)
.
tx_k
;
end
generate
;
chipscope_ila_1
:
chipscope_ila
port
map
(
CONTROL
=>
CONTROL
,
CLK
=>
serdes_phys_i
(
0
)
.
ref_clk
,
TRIG0
=>
TRIG0
,
TRIG1
=>
TRIG1
,
TRIG2
=>
TRIG2
,
TRIG3
=>
TRIG3
);
chipscope_icon_1
:
chipscope_icon
port
map
(
CONTROL0
=>
CONTROL
);
TRIG0
(
1
downto
0
)
<=
detected
;
TRIG0
(
2
)
<=
serdes_phys_i
(
0
)
.
rdy
;
TRIG0
(
4
downto
3
)
<=
serdes_phys_i
(
0
)
.
rx_k
;
TRIG0
(
20
downto
5
)
<=
serdes_phys_i
(
0
)
.
rx_data
;
TRIG0
(
21
)
<=
serdes_phys_i
(
0
)
.
rx_enc_err
;
TRIG1
(
1
downto
0
)
<=
ep_phys_i
(
2
)
.
tx_k
;
TRIG1
(
17
downto
2
)
<=
ep_phys_i
(
2
)
.
tx_data
;
TRIG1
(
18
)
<=
serdes_phys_i
(
2
)
.
tx_disparity
;
TRIG1
(
19
)
<=
serdes_phys_i
(
2
)
.
tx_enc_err
;
TRIG2
(
1
downto
0
)
<=
temp_phys_out
(
2
)
.
tx_k
;
TRIG2
(
17
downto
2
)
<=
temp_phys_out
(
2
)
.
tx_data
;
end
behav
;
top/bare_top/scb_top_bare.vhd
View file @
e3778758
...
...
@@ -425,6 +425,21 @@ architecture rtl of scb_top_bare is
signal
ep_dbg_tx_pcs_rd_array
:
t_ep_dbg_tx_pcs_array
(
g_num_ports
-1
downto
0
);
signal
dbg_chps_id
:
std_logic_vector
(
7
downto
0
);
component
ell
generic
(
g_num_ports
:
integer
:
=
18
);
port
(
-- from endpoints
ep_phys_i
:
in
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
ep_phys_o
:
out
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
-- to serdes
serdes_phys_o
:
out
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
serdes_phys_i
:
in
t_phyif_input_array
(
g_num_ports
-1
downto
0
));
end
component
;
signal
ep_phys_out
:
t_phyif_output_array
(
g_num_ports
-1
downto
0
);
signal
ep_phys_in
:
t_phyif_input_array
(
g_num_ports
-1
downto
0
);
begin
...
...
@@ -674,20 +689,20 @@ begin
pps_csync_p1_i
=>
pps_csync
,
pps_valid_i
=>
pps_valid
,
phy_rst_o
=>
phys_o
(
i
)
.
rst
,
phy_loopen_o
=>
phys_o
(
i
)
.
loopen
,
phy_enable_o
=>
phys_o
(
i
)
.
enable
,
phy_rdy_i
=>
phys_i
(
i
)
.
rdy
,
phy_ref_clk_i
=>
phys_i
(
i
)
.
ref_clk
,
phy_rst_o
=>
ep_phys_out
(
i
)
.
rst
,
phy_loopen_o
=>
ep_phys_out
(
i
)
.
loopen
,
phy_enable_o
=>
ep_phys_out
(
i
)
.
enable
,
phy_rdy_i
=>
ep_phys_in
(
i
)
.
rdy
,
phy_ref_clk_i
=>
ep_phys_in
(
i
)
.
ref_clk
,
phy_tx_data_o
=>
ep_dbg_data_array
(
i
),
-- phys_o(i).tx_data, --
phy_tx_k_o
=>
ep_dbg_k_array
(
i
),
-- phys_o(i).tx_k, --
phy_tx_disparity_i
=>
phys_i
(
i
)
.
tx_disparity
,
phy_tx_enc_err_i
=>
phys_i
(
i
)
.
tx_enc_err
,
phy_rx_data_i
=>
phys_i
(
i
)
.
rx_data
,
phy_rx_clk_i
=>
phys_i
(
i
)
.
rx_clk
,
phy_rx_k_i
=>
phys_i
(
i
)
.
rx_k
,
phy_rx_enc_err_i
=>
phys_i
(
i
)
.
rx_enc_err
,
phy_rx_bitslide_i
=>
phys_i
(
i
)
.
rx_bitslide
,
phy_tx_disparity_i
=>
ep_phys_in
(
i
)
.
tx_disparity
,
phy_tx_enc_err_i
=>
ep_phys_in
(
i
)
.
tx_enc_err
,
phy_rx_data_i
=>
ep_phys_in
(
i
)
.
rx_data
,
phy_rx_clk_i
=>
ep_phys_in
(
i
)
.
rx_clk
,
phy_rx_k_i
=>
ep_phys_in
(
i
)
.
rx_k
,
phy_rx_enc_err_i
=>
ep_phys_in
(
i
)
.
rx_enc_err
,
phy_rx_bitslide_i
=>
ep_phys_in
(
i
)
.
rx_bitslide
,
txtsu_port_id_o
=>
txtsu_timestamps
(
i
)
.
port_id
(
4
downto
0
),
txtsu_frame_id_o
=>
txtsu_timestamps
(
i
)
.
frame_id
,
...
...
@@ -738,8 +753,8 @@ begin
stop_traffic_i
=>
ep_stop_traffic
);
phys_o
(
i
)
.
tx_data
<=
ep_dbg_data_array
(
i
);
phys_o
(
i
)
.
tx_k
<=
ep_dbg_k_array
(
i
);
ep_phys_out
(
i
)
.
tx_data
<=
ep_dbg_data_array
(
i
);
ep_phys_out
(
i
)
.
tx_k
<=
ep_dbg_k_array
(
i
);
ep2tru
(
i
)
.
status
<=
ep_links_up
(
i
);
txtsu_timestamps
(
i
)
.
port_id
(
5
)
<=
'0'
;
...
...
@@ -755,10 +770,23 @@ begin
-- ep2tru(i).rx_pck_class <= (others => '0');
---------------------------
clk_rx_vec
(
i
)
<=
phys_i
(
i
)
.
rx_clk
;
clk_rx_vec
(
i
)
<=
ep_phys_in
(
i
)
.
rx_clk
;
end
generate
gen_endpoints_and_phys
;
U_ELL
:
ell
generic
map
(
g_num_ports
=>
g_num_ports
)
port
map
(
ep_phys_i
=>
ep_phys_out
,
ep_phys_o
=>
ep_phys_in
,
serdes_phys_o
=>
phys_o
,
serdes_phys_i
=>
phys_i
);
--phys_o <= ep_phys_out;
--ep_phys_in <= phys_i;
GEN_TIMING
:
for
I
in
0
to
c_NUM_PORTS
generate
-- improve timing
U_WRF_RXREG_X
:
xwrf_reg
...
...
@@ -967,8 +995,8 @@ begin
gen_no_network_stuff
:
if
(
g_without_network
=
true
)
generate
gen_dummy_resets
:
for
i
in
0
to
g_num_ports
-1
generate
phys_o
(
i
)
.
rst
<=
not
rst_n_periph
;
phys_o
(
i
)
.
loopen
<=
'0'
;
ep_phys_out
(
i
)
.
rst
<=
not
rst_n_periph
;
ep_phys_out
(
i
)
.
loopen
<=
'0'
;
end
generate
gen_dummy_resets
;
end
generate
gen_no_network_stuff
;
...
...
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