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wr-switch-hdl
Commit ceb1897b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top/scb_6ports: new swcore and I2C master for mini-backplane

parent c34c4cc5
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Showing with 34 additions and 7 deletions
top/scb_6ports/scb_top_synthesis.ucf
View file @ ceb1897b
......@@ -157,13 +157,15 @@ NET "gtx_txp_o[5]" LOC="AF1";
NET "gtx_txn_o[5]" LOC="AF2";
NET "mbl_scl_b" LOC="AG32"; #GPIO36
NET "mbl_sda_b" LOC="AF31"; #GPIO37
NET "gtx_sfp_tx_dis_o[0]" LOC="AD29";
NET "gtx_sfp_tx_dis_o[1]" LOC="AA29";
NET "gtx_sfp_tx_dis_o[2]" LOC="AC29";
NET "gtx_sfp_tx_dis_o[3]" LOC="AD31"; #GPIO30
NET "gtx_sfp_tx_dis_o[4]" LOC="AC28"; #GPIO33
NET "gtx_sfp_tx_dis_o[5]" LOC="AG32"; #GPIO36
#NET "gtx_sfp_tx_dis_o[5]" LOC="AG32"; #GPIO36
NET "led_link_o[0]" LOC="AA26"; #GPIO14
NET "led_link_o[1]" LOC="AC30"; #GPIO13
NET "led_link_o[2]" LOC="AA31"; #GPIO11
......@@ -191,9 +193,9 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "fpga_clk_aux_n_i" TNM_NET = fpga_clk_aux_n_i;
TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 16 ns HIGH 50%;
TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 5 ns HIGH 50%;
NET "fpga_clk_aux_p_i" TNM_NET = fpga_clk_aux_p_i;
TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 16 ns HIGH 50%;
TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 5 ns HIGH 50%;
NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
......
top/scb_6ports/scb_top_synthesis.vhd
View file @ ceb1897b
......@@ -120,7 +120,10 @@ entity scb_top_synthesis is
gtx_sfp_tx_dis_o : out std_logic_vector(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0)
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
mbl_scl_b: inout std_logic;
mbl_sda_b: inout std_logic
);
end scb_top_synthesis;
......@@ -209,7 +212,14 @@ architecture Behavioral of scb_top_synthesis is
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_i : in std_logic_vector(31 downto 0) := x"00000000") ;
gpio_i : in std_logic_vector(31 downto 0) := x"00000000";
i2c_mbl0_scl_oen_o : out std_logic;
i2c_mbl0_scl_o : out std_logic;
i2c_mbl0_scl_i : in std_logic := '1';
i2c_mbl0_sda_oen_o : out std_logic;
i2c_mbl0_sda_o : out std_logic;
i2c_mbl0_sda_i : in std_logic := '1'
) ;
end component;
signal to_phys : t_phyif_output_array(g_num_ports-1 downto 0);
......@@ -225,6 +235,11 @@ architecture Behavioral of scb_top_synthesis is
signal top_master_in, bridge_master_in : t_wishbone_master_in;
signal top_master_out, bridge_master_out : t_wishbone_master_out;
signal i2c_mbl0_scl_oen : std_logic;
signal i2c_mbl0_scl_out : std_logic;
signal i2c_mbl0_sda_oen : std_logic;
signal i2c_mbl0_sda_out : std_logic;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
......@@ -247,6 +262,10 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
mbl_scl_b <= i2c_mbl0_scl_out when i2c_mbl0_scl_oen = '0' else 'Z';
mbl_sda_b <= i2c_mbl0_sda_out when i2c_mbl0_sda_oen = '0' else 'Z';
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
......@@ -489,8 +508,14 @@ begin
phys_o => to_phys,
phys_i => from_phys,
led_link_o => led_link_o,
led_act_o => led_act_o);
led_act_o => led_act_o,
i2c_mbl0_scl_oen_o => i2c_mbl0_scl_oen,
i2c_mbl0_scl_o => i2c_mbl0_scl_out,
i2c_mbl0_scl_i => mbl_scl_b,
i2c_mbl0_sda_oen_o => i2c_mbl0_sda_oen,
i2c_mbl0_sda_o => i2c_mbl0_sda_out,
i2c_mbl0_sda_i => mbl_scl_b);
-- end generate gen_with_top;
......
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