Skip to content

W
wr-switch-hdl
Commit 8305d1d1 authored by Maciej Lipinski's avatar Maciej Lipinski
Browse files
Options

swcore: first working swcore with resource_management (needs debugging, simple… 

swcore: first working swcore with resource_management (needs debugging, simple case tested only), output needs resource_management implementation
parent d8e1cd47
Hide whitespace changes
Inline Side-by-side
Showing with 241 additions and 129 deletions
modules/wrsw_swcore/old_allocator/swc_multiport_page_allocator.vhd
View file @ 8305d1d1
......@@ -99,7 +99,10 @@ entity swc_multiport_page_allocator is
-- used only when freeing page,
-- if HIGH then the input resource_i value will be used
-- if LOW then the value read from memory will be used (stored along with usecnt)
free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
force_free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
force_free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
-- number of pages added to the resurce
rescnt_page_num_i : in std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
......@@ -193,6 +196,9 @@ architecture syn of swc_multiport_page_allocator is
--------------------------- resource management ----------------------------------
-- resource number
signal pg_resource_in : std_logic_vector(g_resource_num_width-1 downto 0);
signal pg_alloc_usecnt_resource : std_logic_vector(g_resource_num_width-1 downto 0);
signal pg_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
signal pg_force_free_resource : std_logic_vector(g_resource_num_width-1 downto 0);
signal pg_resource_out : std_logic_vector(g_resource_num_width-1 downto 0);
signal pg_free_resource_valid : std_logic;
signal pg_rescnt_page_num : std_logic_vector(g_page_addr_width-1 downto 0);
......@@ -386,9 +392,16 @@ begin -- syn
-- Resource Manager logic and instantiation
--------------------------------------------------------------------------------------------------
pg_resource_in <= resource_i ((in_sel+1)*g_resource_num_width -1 downto in_sel*g_resource_num_width);
pg_free_resource_valid <= free_resource_valid_i(in_sel);
pg_rescnt_page_num <= rescnt_page_num_i ((in_sel+1)*g_page_addr_width-1 downto in_sel*g_page_addr_width);
pg_alloc_usecnt_resource <= resource_i ((in_sel+1)*g_resource_num_width -1 downto in_sel*g_resource_num_width);
pg_free_resource <= free_resource_i ((in_sel+1)*g_resource_num_width -1 downto in_sel*g_resource_num_width);
pg_force_free_resource <= force_free_resource_i ((in_sel+1)*g_resource_num_width -1 downto in_sel*g_resource_num_width);
pg_resource_in <= pg_force_free_resource when (pg_force_free = '1') else
pg_free_resource when (pg_free = '1') else
pg_alloc_usecnt_resource;
pg_free_resource_valid <= force_free_resource_valid_i(in_sel) when (pg_force_free = '1') else
free_resource_valid_i (in_sel) when (pg_free = '1') else
'0';
pg_rescnt_page_num <= rescnt_page_num_i ((in_sel+1)*g_page_addr_width-1 downto in_sel*g_page_addr_width);
MUX2: process(clk_i)
......
modules/wrsw_swcore/old_allocator/swc_page_alloc_old.vhd
View file @ 8305d1d1
......@@ -283,7 +283,7 @@ architecture syn of swc_page_allocator is
signal res_mgr_alloc : std_logic;
signal res_mgr_free : std_logic;
signal res_mgr_rescnt_page_num : std_logic_vector(g_resource_num_width-1 downto 0);
signal res_mgr_res_num : std_logic_vector(g_resource_num_width-1 downto 0);
signal res_mgr_rescnt_set : std_logic;
-----------------------------
......@@ -655,7 +655,8 @@ begin -- syn
res_mgr_alloc <= alloc_i and done;
res_mgr_free <= ((free_i and free_last_usecnt) or force_free_i) and done;
res_mgr_rescnt_page_num <= resource_i when (free_resource_valid_i='1') else rescnt_mem_rddata;
res_mgr_res_num <= rescnt_mem_rddata when (free_resource_valid_i='0' and (free_i='1' or force_free_i='1')) else
resource_i;
res_mgr_rescnt_set <= set_usecnt_i and done;
------ resource management
......@@ -673,7 +674,7 @@ begin -- syn
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
resource_i => resource_i,
resource_i => res_mgr_res_num,
alloc_i => res_mgr_alloc,
free_i => res_mgr_free,
rescnt_set_i => res_mgr_rescnt_set,
......
modules/wrsw_swcore/swc_multiport_pck_pg_free_module.vhd
View file @ 8305d1d1
......@@ -53,35 +53,41 @@ entity swc_multiport_pck_pg_free_module is
g_num_ports : integer ; --:= c_swc_num_ports
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
g_data_width : integer
g_data_width : integer ;
g_resource_num_width : integer
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ib_force_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ib_force_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ob_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ob_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ob_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ob_free_i : in std_logic_vector(g_num_ports-1 downto 0);
ob_free_done_o : out std_logic_vector(g_num_ports-1 downto 0);
ob_free_pgaddr_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_num_ports * g_data_width - 1 downto 0);
--ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0)
ll_read_addr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_num_ports * g_data_width - 1 downto 0);
--ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0)
);
end swc_multiport_pck_pg_free_module;
......@@ -97,36 +103,42 @@ begin -- syn
LPD: swc_pck_pg_free_module
generic map(
g_page_addr_width => g_page_addr_width,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
g_data_width => g_data_width
g_page_addr_width => g_page_addr_width,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
g_data_width => g_data_width,
g_resource_num_width => g_resource_num_width
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
clk_i => clk_i,
rst_n_i => rst_n_i,
ib_force_free_i => ib_force_free_i(i),
ib_force_free_done_o => ib_force_free_done_o(i),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ib_force_free_i => ib_force_free_i(i),
ib_force_free_done_o => ib_force_free_done_o(i),
ib_force_free_pgaddr_i => ib_force_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ob_free_i => ob_free_i(i),
ob_free_done_o => ob_free_done_o(i),
ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ob_free_i => ob_free_i(i),
ob_free_done_o => ob_free_done_o(i),
ob_free_pgaddr_i => ob_free_pgaddr_i((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_addr_o => ll_read_addr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_data_i => ll_read_data_i((i+1)*g_data_width - 1 downto i * g_data_width),
ll_read_req_o => ll_read_req_o(i),
ll_read_valid_data_i => ll_read_valid_data_i(i),
mmu_free_o => mmu_free_o(i),
mmu_free_done_i => mmu_free_done_i(i),
mmu_free_last_usecnt_i => mmu_free_last_usecnt_i(i),
mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
mmu_force_free_o => mmu_force_free_o(i),
mmu_force_free_done_i => mmu_force_free_done_i(i),
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width)
ll_read_addr_o => ll_read_addr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
ll_read_data_i => ll_read_data_i((i+1)*g_data_width - 1 downto i * g_data_width),
ll_read_req_o => ll_read_req_o(i),
ll_read_valid_data_i => ll_read_valid_data_i(i),
mmu_resource_i => mmu_resource_i((i+1)*g_resource_num_width -1 downto i *g_resource_num_width),
mmu_free_o => mmu_free_o(i),
mmu_free_done_i => mmu_free_done_i(i),
mmu_free_last_usecnt_i => mmu_free_last_usecnt_i(i),
mmu_free_pgaddr_o => mmu_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
mmu_free_resource_o => mmu_free_resource_o((i+1)*g_resource_num_width -1 downto i *g_resource_num_width),
mmu_free_resource_valid_o => mmu_free_resource_valid_o(i),
mmu_force_free_o => mmu_force_free_o(i),
mmu_force_free_done_i => mmu_force_free_done_i(i),
mmu_force_free_pgaddr_o => mmu_force_free_pgaddr_o((i+1)*g_page_addr_width - 1 downto i * g_page_addr_width),
mmu_force_free_resource_o => mmu_force_free_resource_o((i+1)*g_resource_num_width -1 downto i *g_resource_num_width),
mmu_force_free_resource_valid_o => mmu_force_free_resource_valid_o(i)
);
end generate lpd_gen;
......
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
View file @ 8305d1d1
......@@ -55,33 +55,40 @@ entity swc_pck_pg_free_module is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
g_data_width : integer
g_data_width : integer ;
g_resource_num_width : integer
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic;
ib_force_free_done_o : out std_logic;
ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ib_force_free_i : in std_logic;
ib_force_free_done_o : out std_logic;
ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ob_free_i : in std_logic;
ob_free_done_o : out std_logic;
ob_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ob_free_i : in std_logic;
ob_free_done_o : out std_logic;
ob_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_data_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_last_usecnt_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_data_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_resource_i : in std_logic_vector(g_resource_num_width -1 downto 0);
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_last_usecnt_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
mmu_free_resource_valid_o : out std_logic;
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic
);
......@@ -125,8 +132,16 @@ architecture syn of swc_pck_pg_free_module is
signal ones : std_logic_vector(g_page_addr_width - 1 downto 0);
signal freeing_mode : std_logic_vector(1 downto 0);
signal fifo_clear_n : std_logic;
signal eof : std_logic;
signal fifo_clear_n : std_logic;
signal eof : std_logic;
signal free_resource : std_logic_vector(g_resource_num_width -1 downto 0);
signal free_resource_valid : std_logic;
signal force_free_resource : std_logic_vector(g_resource_num_width -1 downto 0);
signal force_free_resource_valid : std_logic;
begin -- syn
......@@ -219,6 +234,12 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_free <= '0';
freeing_mode <= (others => '0');
eof <= '0';
free_resource <= (others => '0');
free_resource_valid <= '0';
force_free_resource <= (others => '0');
force_free_resource_valid <= '0';
--================================================
else
......@@ -231,6 +252,11 @@ fsm_force_free : process(clk_i, rst_n_i)
mmu_force_free <= '0';
mmu_free <= '0';
eof <= '0';
free_resource <= (others => '0');
free_resource_valid <= '0';
force_free_resource <= (others => '0');
force_free_resource_valid <= '0';
if(fifo_empty = '0') then
fifo_rd <= '1';
......@@ -309,6 +335,13 @@ fsm_force_free : process(clk_i, rst_n_i)
--current_page <= next_page;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
-- the first page only
if(free_resource_valid = '0') then
free_resource <= mmu_resource_i ;
free_resource_valid <= '1';
end if;
end if;
end if;
......@@ -329,6 +362,12 @@ fsm_force_free : process(clk_i, rst_n_i)
--current_page <= next_page;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
-- the first page only
if(free_resource_valid = '0') then
free_resource <= mmu_resource_i ;
free_resource_valid <= '1';
end if;
end if;
end if;
......@@ -363,5 +402,11 @@ fsm_force_free : process(clk_i, rst_n_i)
ib_force_free_done_o <= ib_force_free_done;
ob_free_done_o <= ob_free_done;
mmu_free_resource_o <= free_resource;
mmu_free_resource_valid_o <= free_resource_valid;
mmu_force_free_resource_o <= force_free_resource;
mmu_force_free_resource_valid_o <= force_free_resource_valid;
end syn;
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ 8305d1d1
......@@ -231,7 +231,7 @@ package swc_swcore_pkg is
mmu_nomem_i : in std_logic;
--- management
mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
-- mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
mmu_resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
mmu_rescnt_page_num_o : out std_logic_vector(g_page_addr_width-1 downto 0);
mmu_res_almost_full_i : in std_logic_vector(g_resource_num -1 downto 0);
......@@ -306,7 +306,10 @@ package swc_swcore_pkg is
nomem_o : out std_logic;
resource_i : in std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
resource_o : out std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
force_free_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width - 1 downto 0);
force_free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
rescnt_page_num_i : in std_logic_vector(g_num_ports * g_page_addr_width-1 downto 0);
res_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
res_almost_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0)
......@@ -459,7 +462,8 @@ component swc_multiport_pck_pg_free_module is
g_num_ports : integer ; --:= c_swc_num_ports
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
g_data_width : integer
g_data_width : integer ;
g_resource_num_width : integer
);
port (
clk_i : in std_logic;
......@@ -479,14 +483,20 @@ component swc_multiport_pck_pg_free_module is
ll_read_req_o : out std_logic_vector(g_num_ports-1 downto 0);
ll_read_valid_data_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_resource_i : in std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0)
mmu_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_last_usecnt_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_o : out std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_done_i : in std_logic_vector(g_num_ports-1 downto 0);
mmu_force_free_pgaddr_o : out std_logic_vector(g_num_ports * g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_num_ports * g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic_vector(g_num_ports-1 downto 0)
);
end component;
......@@ -494,7 +504,8 @@ component swc_multiport_pck_pg_free_module is
generic(
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_pck_pg_free_fifo_size : integer ;--:= c_swc_freeing_fifo_size
g_data_width : integer
g_data_width : integer ;
g_resource_num_width : integer
);
port (
clk_i : in std_logic;
......@@ -513,14 +524,20 @@ component swc_multiport_pck_pg_free_module is
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_free_last_usecnt_i : in std_logic;
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
mmu_resource_i : in std_logic_vector(g_resource_num_width -1 downto 0);
mmu_free_o : out std_logic;
mmu_free_done_i : in std_logic;
mmu_free_last_usecnt_i : in std_logic;
mmu_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
mmu_free_resource_valid_o : out std_logic;
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
mmu_force_free_resource_o : out std_logic_vector(g_resource_num_width -1 downto 0);
mmu_force_free_resource_valid_o : out std_logic
);
end component;
......@@ -659,7 +676,7 @@ package body swc_swcore_pkg is
rtu_broadcast: std_logic;
res_num_width: integer) return std_logic_vector is
variable tmp : std_logic_vector(7 downto 0); -- assuming max resource number of 8 (far over-estimated)
variable ones : std_logic_vector(rtu_prio'length downto 0);
variable ones : std_logic_vector(rtu_prio'length - 1 downto 0);
begin
ones := (others => '0');
---------- the mapping as you please ------------------
......@@ -685,13 +702,21 @@ package body swc_swcore_pkg is
tmp_prio(9 downto rtu_prio'length) := (others => '0');
tmp_prio(rtu_prio'length-1 downto 0 ) := rtu_prio;
if(resource = res2(resource'length -1 downto 0)) then
tmp := to_unsigned(0,tmp'length );
tmp := to_unsigned(7,tmp'length );
else
if(unsigned(tmp_prio) + 1 >= to_unsigned(queue_num,9)) then
tmp := to_unsigned(queue_num,tmp'length);
if(unsigned(tmp_prio) > to_unsigned(0,9)) then
tmp := to_unsigned(0,tmp'length);
else
tmp := unsigned(tmp_prio) + 1;
tmp := unsigned(tmp_prio) - 1;
end if;
-- if(unsigned(tmp_prio) + 1 >= to_unsigned(queue_num,9)) then
-- tmp := to_unsigned(queue_num,tmp'length);
-- else
-- tmp := unsigned(tmp_prio) + 1;
-- end if;
end if;
return std_logic_vector(tmp);
end function;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ 8305d1d1
......@@ -299,13 +299,18 @@ architecture rtl of xswc_core is
signal tap : std_logic_vector(127 downto 0);
signal ppfm2mmu_free_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
signal ppfm2mmu_free_resource_valid : std_logic_vector(g_num_ports -1 downto 0);
signal ppfm2mmu_force_free_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
signal ppfm2mmu_force_free_resource_valid : std_logic_vector(g_num_ports -1 downto 0);
signal mmu2ppfm_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block (IB) << with >>Page allocator (MMU)<< -- resource management
----------------------------------------------------------------------------------------------------
signal mmu2ib_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
signal ib2mmu_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
signal ib2mmu_free_resource_valid : std_logic_vector(g_num_ports -1 downto 0);
signal ib2mmu_rescnt_page_num : std_logic_vector(g_num_ports*c_mpm_page_addr_width -1 downto 0);
signal mmu2ib_res_full : std_logic_vector(g_num_ports*c_res_mmu_resource_num -1 downto 0);
signal mmu2ib_res_almost_full : std_logic_vector(g_num_ports*c_res_mmu_resource_num -1 downto 0);
......@@ -372,9 +377,8 @@ architecture rtl of xswc_core is
mmu_pageaddr_o => ib_pageaddr_output((i + 1) * c_mpm_page_addr_width - 1 downto i * c_mpm_page_addr_width),
-- resource management
mmu_resource_i => mmu2ib_resource ((i+1)*c_res_mmu_resource_num_width -1 downto i*c_res_mmu_resource_num_width),
-- mmu_resource_i => mmu2ib_resource ((i+1)*c_res_mmu_resource_num_width -1 downto i*c_res_mmu_resource_num_width),
mmu_resource_o => ib2mmu_resource ((i+1)*c_res_mmu_resource_num_width -1 downto i*c_res_mmu_resource_num_width),
-- mmu_free_resource_valid_o=> ib2mmu_free_resource_valid(i),
mmu_rescnt_page_num_o => ib2mmu_rescnt_page_num ((i+1)*c_mpm_page_addr_width -1 downto i*c_mpm_page_addr_width),
mmu_res_full_i => mmu2ib_res_full ((i+1)*c_res_mmu_resource_num -1 downto i*c_res_mmu_resource_num),
mmu_res_almost_full_i => mmu2ib_res_almost_full ((i+1)*c_res_mmu_resource_num -1 downto i*c_res_mmu_resource_num),
......@@ -500,36 +504,43 @@ architecture rtl of xswc_core is
PCK_PAGES_FREEEING_MODULE: swc_multiport_pck_pg_free_module
generic map(
g_num_ports => g_num_ports,
g_page_addr_width => c_mpm_page_addr_width,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
g_data_width => c_ll_data_width
g_num_ports => g_num_ports,
g_page_addr_width => c_mpm_page_addr_width,
g_pck_pg_free_fifo_size => g_pck_pg_free_fifo_size,
g_data_width => c_ll_data_width,
g_resource_num_width => c_res_mmu_resource_num_width
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
clk_i => clk_i,
rst_n_i => rst_n_i,
ib_force_free_i => ib_force_free,
ib_force_free_done_o => ppfm_force_free_done_to_ib,
ib_force_free_pgaddr_i => ib_force_free_pgaddr,
ib_force_free_i => ib_force_free,
ib_force_free_done_o => ppfm_force_free_done_to_ib,
ib_force_free_pgaddr_i => ib_force_free_pgaddr,
ob_free_i => ob_free,
ob_free_done_o => ppfm_free_done_to_ob,
ob_free_pgaddr_i => ob_free_pgaddr,
ob_free_i => ob_free,
ob_free_done_o => ppfm_free_done_to_ob,
ob_free_pgaddr_i => ob_free_pgaddr,
ll_read_addr_o => fp2ll_addr, --ppfm_read_addr,
ll_read_data_i => ll2fp_data, --ll_data,
ll_read_req_o => fp2ll_rd_req, --ppfm_read_req,
ll_read_valid_data_i => ll2fp_read_done, --ll_read_valid_data,
ll_read_addr_o => fp2ll_addr, --ppfm_read_addr,
ll_read_data_i => ll2fp_data, --ll_data,
ll_read_req_o => fp2ll_rd_req, --ppfm_read_req,
ll_read_valid_data_i => ll2fp_read_done, --ll_read_valid_data,
mmu_force_free_o => ppfm_force_free,
mmu_force_free_done_i => mmu_force_free_done,
mmu_force_free_pgaddr_o => ppfm_force_free_pgaddr,
mmu_resource_i => mmu2ppfm_resource,
mmu_force_free_o => ppfm_force_free,
mmu_force_free_done_i => mmu_force_free_done,
mmu_force_free_pgaddr_o => ppfm_force_free_pgaddr,
mmu_free_resource_o => ppfm2mmu_free_resource,
mmu_free_resource_valid_o => ppfm2mmu_free_resource_valid,
mmu_free_o => ppfm_free,
mmu_free_done_i => mmu_free_done,
mmu_free_pgaddr_o => ppfm_free_pgaddr,
mmu_free_last_usecnt_i => mmu2ppfm_free_last_usecnt
mmu_free_o => ppfm_free,
mmu_free_done_i => mmu_free_done,
mmu_free_pgaddr_o => ppfm_free_pgaddr,
mmu_free_last_usecnt_i => mmu2ppfm_free_last_usecnt,
mmu_force_free_resource_o => ppfm2mmu_force_free_resource,
mmu_force_free_resource_valid_o => ppfm2mmu_force_free_resource_valid
);
......@@ -610,8 +621,13 @@ architecture rtl of xswc_core is
nomem_o => mmu_nomem,
--------------------------- resource management ----------------------------------
resource_i => ib2mmu_resource,
resource_o => mmu2ib_resource,
free_resource_valid_i => ib2mmu_free_resource_valid,
resource_o => mmu2ppfm_resource,
free_resource_i => ppfm2mmu_free_resource,
free_resource_valid_i => ppfm2mmu_free_resource_valid,
force_free_resource_i => ppfm2mmu_force_free_resource,
force_free_resource_valid_i=> ppfm2mmu_force_free_resource_valid,
rescnt_page_num_i => ib2mmu_rescnt_page_num,
res_full_o => mmu2ib_res_full,
res_almost_full_o => mmu2ib_res_almost_full
......
modules/wrsw_swcore/xswc_input_block.vhd
View file @ 8305d1d1
......@@ -168,7 +168,7 @@ entity xswc_input_block is
--------------------------- resource management ----------------------------------
-- resource number
mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
--mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
-- outputed when freeing
mmu_resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment