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wr-switch-hdl
Commit 747d1744 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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modules/wrsw_swcore/Manifest.py
View file @ 747d1744
......@@ -9,16 +9,23 @@
files = [
"swc_swcore_pkg.vhd",
"swc_rd_wr_ram.vhd",
"swc_core.vhd",
"swc_multiport_linked_list.vhd",
"swc_multiport_page_allocator.vhd",
"new_allocator_generic_rams/swc_multiport_page_allocator.vhd",
"new_allocator_generic_rams/swc_page_alloc.vhd",
#"swc_multiport_page_allocator.vhd",
#"swc_page_alloc_old.vhd",
"swc_multiport_pck_pg_free_module.vhd",
"swc_ob_prio_queue.vhd",
#"swc_packet_mem.vhd",
#"swc_packet_mem_read_pump.vhd",
#"swc_packet_mem_write_pump.vhd",
#"swc_page_alloc.vhd",
"swc_page_alloc_old.vhd",
"swc_pck_pg_free_module.vhd",
"swc_pck_transfer_arbiter.vhd",
"swc_pck_transfer_input.vhd",
......@@ -30,5 +37,8 @@ files = [
"xswc_input_block.vhd",
"../wrsw_shared_types_pkg.vhd",
"swc_ll_read_data_validation.vhd",
]
modules = modules = {"local": ["mpm"]}
\ No newline at end of file
"buggy_ram_synth.vhd"];
#"buggy_ram.vhd",
#"buggy_ram.ngc"]
modules = modules = {"local": ["mpm"]}
modules/wrsw_swcore/swc_multiport_linked_list.vhd
View file @ 747d1744
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-26
-- Last update: 2012-03-12
-- Last update: 2012-03-18
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -53,13 +53,13 @@ use work.gencores_pkg.all;
entity swc_multiport_linked_list is
generic (
g_num_ports : integer; --:= c_swc_num_ports
g_addr_width : integer; --:= c_swc_page_addr_width;
g_page_num : integer; --:= c_swc_packet_mem_num_pages
g_num_ports : integer := 7; --:= c_swc_num_ports
g_addr_width : integer := 10; --:= c_swc_page_addr_width;
g_page_num : integer := 1024; --:= c_swc_packet_mem_num_pages
-- new stuff
g_size_width : integer ;
g_partial_select_width : integer ;
g_data_width : integer --:= c_swc_packet_mem_num_pages + 2
g_size_width : integer := 10;
g_partial_select_width : integer := 1;
g_data_width : integer := 18 --:= c_swc_packet_mem_num_pages + 2
----------------------------------------------------------------------------------------
-- the following relation is needed for the things to work
......@@ -194,54 +194,78 @@ begin -- syn
zeros <= (others => '0');
-- this memory is read by the output of the MPM (called read pump)
PAGE_INDEX_LINKED_LIST_MPM : generic_dpram
generic map (
g_data_width => g_data_width,-- one bit for validating the data
g_size => g_page_num,
g_dual_clock=> false
)
port map (
-- Port A -- writing
clka_i => clk_i,
bwea_i => (others => '1'),
wea_i => ll_wr_ena_reg,
aa_i => ll_wr_addr_reg,
da_i => ll_wr_data_reg,
qa_o => open,
PAGE_INDEX_LINKED_LIST_MPM: swc_rd_wr_ram
generic map (
g_data_width => g_data_width,-- one bit for validating the data
g_size => g_page_num)
port map (
clk_i => clk_i,
we_i => ll_wr_ena_reg,
wa_i => ll_wr_addr_reg,
wd_i => ll_wr_data_reg,
ra_i => mpm_rpath_addr_i,
rd_o => mpm_rpath_data_o);
---- this memory is read by the output of the MPM (called read pump)
--PAGE_INDEX_LINKED_LIST_MPM : generic_dpram
-- generic map (
-- g_data_width => g_data_width,-- one bit for validating the data
-- g_size => g_page_num,
-- g_dual_clock=> false
-- )
-- port map (
-- -- Port A -- writing
-- clka_i => clk_i,
-- bwea_i => (others => '1'),
-- wea_i => ll_wr_ena_reg,
-- aa_i => ll_wr_addr_reg,
-- da_i => ll_wr_data_reg,
-- qa_o => open,
-- Port B -- reading
clkb_i => clk_i,
bweb_i => (others => '1'),
web_i => '0',
ab_i => mpm_rpath_addr_i,
db_i => (others => '0'),
qb_o => mpm_rpath_data_o
);
-- this memory is read by the process that force-frees pck on error
PAGE_INDEX_LINKED_LIST_FREE_PCK : generic_dpram
generic map (
g_data_width => g_data_width,-- one bit for validating the data
g_size => g_page_num
)
port map (
-- Port A -- writing
clka_i => clk_i,
bwea_i => (others => '1'),
wea_i => ll_wr_ena_reg,
aa_i => ll_wr_addr_reg,
da_i => ll_wr_data_reg,
qa_o => open,
-- -- Port B -- reading
-- clkb_i => clk_i,
-- bweb_i => (others => '1'),
-- web_i => '0',
-- ab_i => mpm_rpath_addr_i,
-- db_i => (others => '0'),
-- qb_o => mpm_rpath_data_o
-- );
PAGE_INDEX_LINKED_LIST_FREE_PCK: swc_rd_wr_ram
generic map (
g_data_width => g_data_width,
g_size => g_page_num)
port map (
clk_i => clk_i,
we_i => ll_wr_ena_reg,
wa_i => ll_wr_addr_reg,
wd_i => ll_wr_data_reg,
ra_i => ll_free_pck_addr,
rd_o => ll_free_pck_data);
---- this memory is read by the process that force-frees pck on error
--PAGE_INDEX_LINKED_LIST_FREE_PCK : generic_dpram
-- generic map (
-- g_data_width => g_data_width,-- one bit for validating the data
-- g_size => g_page_num
-- )
-- port map (
-- -- Port A -- writing
-- clka_i => clk_i,
-- bwea_i => (others => '1'),
-- wea_i => ll_wr_ena_reg,
-- aa_i => ll_wr_addr_reg,
-- da_i => ll_wr_data_reg,
-- qa_o => open,
-- Port B -- reading
clkb_i => clk_i,
bweb_i => (others => '1'),
web_i => '0',
ab_i => ll_free_pck_addr,
db_i => (others => '0'),
qb_o => ll_free_pck_data
);
-- -- Port B -- reading
-- clkb_i => clk_i,
-- bweb_i => (others => '1'),
-- web_i => '0',
-- ab_i => ll_free_pck_addr,
-- db_i => (others => '0'),
-- qb_o => ll_free_pck_data
-- );
gen_write_request_vec : for i in 0 to g_num_ports - 1 generate
tmp_write_end_of_list(i) <= write_data_i((i + 1) * g_data_width - 2);
......
modules/wrsw_swcore/swc_page_alloc_old.vhd
View file @ 747d1744
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 2011-03-15
-- Last update: 2012-03-18
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -104,12 +104,12 @@ use work.genram_pkg.all;
entity swc_page_allocator is
generic (
-- number of pages we consider
g_num_pages : integer := 2048;
g_num_pages : integer := 1024;
-- number of bits of the page address
g_page_addr_width: integer := 11; --g_page_addr_bits
g_page_addr_width: integer := 10; --g_page_addr_bits
g_num_ports : integer ;--:= c_swc_num_ports
g_num_ports : integer := 7;--:= c_swc_num_ports
-- number of bits of the user count value
g_usecount_width: integer := 4 --g_use_count_bits
......@@ -275,53 +275,80 @@ begin -- syn
out_o => l0_first_free);
L0_LUT : generic_dpram
generic map (
g_data_width => 32,
-- g_addr_bits => c_l1_bitmap_addrbits,
g_size => c_l1_bitmap_size,
g_dual_clock => false)
port map (
clka_i => clk_i,
clkb_i => clk_i,
--L0_LUT : generic_dpram
-- generic map (
-- g_data_width => 32,
-- -- g_addr_bits => c_l1_bitmap_addrbits,
-- g_size => c_l1_bitmap_size,
-- g_dual_clock => false,
-- g_addr_conflict_resolution => "read_first")
-- port map (
-- clka_i => clk_i,
-- clkb_i => clk_i,
aa_i => l0_wr_addr,
da_i => l0_wr_data,
qa_o => open,
bwea_i => x"0",
wea_i => l0_wr,
-- aa_i => l0_wr_addr,
-- da_i => l0_wr_data,
-- qa_o => open,
-- bwea_i => x"0",
-- wea_i => l0_wr,
ab_i => l0_rd_addr,
db_i => x"00000000",
qb_o => l0_rd_data,
bweb_i => x"0",
web_i => '0');
-- ab_i => l0_rd_addr,
-- db_i => x"00000000",
-- qb_o => l0_rd_data,
-- bweb_i => x"0",
-- web_i => '0');
L0_UCNTMEM : generic_dpram
L0_LUT: swc_rd_wr_ram
generic map (
g_data_width => 32,
g_size => c_l1_bitmap_size,
g_use_native => true)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
we_i => l0_wr,
wa_i => l0_wr_addr,
wd_i => l0_wr_data,
ra_i => l0_rd_addr,
rd_o => l0_rd_data);
-- L0_UCNTMEM : generic_dpram
-- generic map (
-- g_data_width => g_usecount_width,
---- g_addr_bits => g_page_addr_width,
-- g_size => g_num_pages,
-- g_dual_clock => false,
-- g_addr_conflict_resolution => "read_first")
-- port map (
-- clka_i => clk_i,
-- clkb_i => clk_i,
-- da_i => usecnt_mem_wrdata,
-- aa_i => usecnt_mem_wraddr,
-- qa_o => open,
-- wea_i => usecnt_mem_wr,
-- bwea_i => ones((g_usecount_width+7)/8 -1 downto 0),--ones((g_usecount_width+7)/8 -1 downto 0),
-- ab_i => usecnt_mem_rdaddr,
-- qb_o => usecnt_mem_rddata,
-- db_i => ones(g_usecount_width-1 downto 0),
-- bweb_i => ones((g_usecount_width+7)/8-1 downto 0), --ones((g_usecount_width+7)/8-1 downto 0),
-- web_i => '0'
-- );
L0_UCNTMEM: swc_rd_wr_ram
generic map (
g_data_width => g_usecount_width,
-- g_addr_bits => g_page_addr_width,
g_size => g_num_pages)
port map (
clka_i => clk_i,
clkb_i => clk_i,
da_i => usecnt_mem_wrdata,
aa_i => usecnt_mem_wraddr,
qa_o => open,
wea_i => usecnt_mem_wr,
bwea_i => ones((g_usecount_width+7)/8 -1 downto 0),--ones((g_usecount_width+7)/8 -1 downto 0),
ab_i => usecnt_mem_rdaddr,
qb_o => usecnt_mem_rddata,
db_i => ones(g_usecount_width-1 downto 0),
bweb_i => ones((g_usecount_width+7)/8-1 downto 0), --ones((g_usecount_width+7)/8-1 downto 0),
web_i => '0'
);
clk_i => clk_i,
rst_n_i => rst_n_i,
we_i => usecnt_mem_wr,
wa_i => usecnt_mem_wraddr,
wd_i => usecnt_mem_wrdata,
ra_i => usecnt_mem_rdaddr,
rd_o => usecnt_mem_rddata);
fsm : process(clk_i, rst_n_i)
-- variable l:line;
......
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ 747d1744
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 2012-03-15
-- Last update: 2012-03-18
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -47,6 +47,8 @@ use ieee.math_real.log2;
library work;
use work.wr_fabric_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.genram_pkg.all;
package swc_swcore_pkg is
......@@ -70,6 +72,20 @@ package swc_swcore_pkg is
zero_o : out std_logic);
end component;
component swc_rd_wr_ram
generic (
g_data_width : integer;
g_size : integer;
g_use_native : boolean := true);
port (
clk_i : in std_logic;
rst_n_i : in std_logic := '1';
we_i : in std_logic;
wa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
wd_i : in std_logic_vector(g_data_width-1 downto 0);
ra_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
rd_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component swc_page_allocator
generic (
......
modules/wrsw_swcore/xswc_output_block.vhd
View file @ 747d1744
......@@ -424,28 +424,41 @@ begin -- behavoural
-- onehot_o => drop_array,
-- out_o => drop_index);
PRIO_QUEUE : generic_dpram
PRIO_QUEUE: swc_rd_wr_ram
generic map (
g_data_width => g_mpm_page_addr_width, -- + g_max_pck_size_width,
g_size => (g_prio_num * g_output_block_per_prio_fifo_size)
)
g_size => (g_prio_num * g_output_block_per_prio_fifo_size))
port map (
-- Port A -- writing
clka_i => clk_i,
bwea_i => (others => '1'), --ram_ones,
wea_i => wr_en_reg,
aa_i => wr_addr_reg,
da_i => wr_data_reg,
qa_o => open,
-- Port B -- reading
clkb_i => clk_i,
bweb_i => (others => '1'), --ram_ones,
web_i => '0',
ab_i => rd_addr, -- drop_imp : ram_rd_addr,
db_i => (others => '0'), --ram_zeros,
qb_o => rd_data
);
clk_i => clk_i,
we_i => wr_en_reg,
wa_i => wr_addr_reg,
wd_i => wr_data_reg,
ra_i => rd_addr,
rd_o => rd_data);
--PRIO_QUEUE : generic_dpram
-- generic map (
-- g_data_width => g_mpm_page_addr_width, -- + g_max_pck_size_width,
-- g_size => (g_prio_num * g_output_block_per_prio_fifo_size)
-- )
-- port map (
-- -- Port A -- writing
-- clka_i => clk_i,
-- bwea_i => (others => '1'), --ram_ones,
-- wea_i => wr_en_reg,
-- aa_i => wr_addr_reg,
-- da_i => wr_data_reg,
-- qa_o => open,
-- -- Port B -- reading
-- clkb_i => clk_i,
-- bweb_i => (others => '1'), --ram_ones,
-- web_i => '0',
-- ab_i => rd_addr, -- drop_imp : ram_rd_addr,
-- db_i => (others => '0'), --ram_zeros,
-- qb_o => rd_data
-- );
wr_ram : process(clk_i, rst_n_i)
......
testbench/scb_top/main.sv
View file @ 747d1744
......@@ -20,7 +20,7 @@ module main;
reg clk_swc_mpm_core=0;
reg rst_n=0;
parameter g_num_ports = 15;
parameter g_num_ports = 6;
// prameters to create some gaps between pks (not work really well)
parameter g_enable_pck_gaps = 0; //1=TRUE, 0=FALSE
......@@ -30,7 +30,8 @@ module main;
// defining which ports send pcks -> forwarding is one-to-one
// (port_1 to port_14, port_2 to port_13, etc)
reg [15:0] portUnderTest = 16'b0010101010101010;
reg [15:0] portUnderTest = 16'b0000000011111111;
/* -----\/----- EXCLUDED -----\/-----
tbi_clock_rst_gen
......@@ -228,8 +229,11 @@ module main;
for (int dd=0;dd<g_num_ports;dd++)
begin
rtu.set_port_config(dd, 1, 1, 1);
rtu.add_static_rule('{dd, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<dd));
end
rtu.add_static_rule('{5, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<2 ));
rtu.add_static_rule('{6, 'h50, 'hca, 'hfe, 'hba, 'hbe}, (1<<1 ));
// rtu.set_hash_poly();
def_vlan.port_mask = 32'hffffffff;
......@@ -243,166 +247,28 @@ module main;
rtu.enable();
////////////// sending packest on all the ports (16) according to the portUnderTest mask.///////
fork
begin
if(portUnderTest[15])
begin
for(int i=0;i<20;i++)
begin
$display("Try f_1:%d", i);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[15].send /* src */, ports[0].recv /* sink */, 15/* srcPort */ , 0 /* dstPort */);
end
end
end
begin
if(portUnderTest[14])
begin
for(int i=0;i<20;i++)
begin
$display("Try f_1:%d", i);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[14].send /* src */, ports[1].recv /* sink */, 14/* srcPort */ , 1 /* dstPort */);
end
end
end
begin
if(portUnderTest[13])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_2:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[13].send /* src */, ports[2].recv /* sink */, 13 /* srcPort */ , 2 /* dstPort */);
end
end
end
begin
if(portUnderTest[12])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_3:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[12].send /* src */, ports[3].recv /* sink */, 12 /* srcPort */ , 3 /* dstPort */);
end
end
end
begin
if(portUnderTest[11])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_4:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[11].send /* src */, ports[4].recv /* sink */, 11 /* srcPort */ , 4 /* dstPort */);
end
end
end
begin
if(portUnderTest[10])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_4:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[10].send /* src */, ports[5].recv /* sink */, 10 /* srcPort */ , 5 /* dstPort */);
end
end
end
begin
if(portUnderTest[9])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_5:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[9].send /* src */, ports[6].recv /* sink */, 9 /* srcPort */ , 6 /* dstPort */);
end
end
end
begin
if(portUnderTest[8])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[8].send /* src */, ports[7].recv /* sink */, 8 /* srcPort */ , 7 /* dstPort */);
end
end
end
begin
if(portUnderTest[7])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[7].send /* src */, ports[8].recv /* sink */, 7 /* srcPort */ , 8 /* dstPort */);
end
end
end
begin
if(portUnderTest[6])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[6].send /* src */, ports[9].recv /* sink */, 6 /* srcPort */ , 9 /* dstPort */);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[6].send /* src */, ports[1].recv /* sink */, 6 /* srcPort */ , 1 /* dstPort */);
end
end
end
end // fork begin
`ifdef none
begin
if(portUnderTest[5])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[5].send /* src */, ports[10].recv /* sink */, 5 /* srcPort */ , 10 /* dstPort */);
end
end
end
begin
if(portUnderTest[4])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[4].send /* src */, ports[11].recv /* sink */, 4 /* srcPort */ , 11 /* dstPort */);
end
end
end
begin
if(portUnderTest[3])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[3].send /* src */, ports[12].recv /* sink */, 3 /* srcPort */ , 12 /* dstPort */);
end
end
end
begin
if(portUnderTest[2])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[2].send /* src */, ports[13].recv /* sink */, 2 /* srcPort */ , 13 /* dstPort */);
end
end
end
begin
if(portUnderTest[1])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[1].send /* src */, ports[14].recv /* sink */, 1 /* srcPort */ , 14 /* dstPort */);
end
end
end
begin
if(portUnderTest[0])
begin
for(int g=0;g<20;g++)
begin
$display("Try f_6:%d", g);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[0].send /* src */, ports[15].recv /* sink */, 0 /* srcPort */ , 15 /* dstPort */);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[5].send /* src */, ports[2] .recv /* sink */, 5 /* srcPort */ , 2 /* dstPort */);
end
end
end
`endif
forever begin
nic.update(DUT.U_Top.U_Wrapped_SCBCore.vic_irqs[0]);
@(posedge clk_sys);
......
testbench/scb_top/scb_top_sim_svwrap.svh
View file @ 747d1744
......@@ -48,7 +48,7 @@ module scb_top_sim_svwrap
clk_swc_mpm_core_i
);
parameter g_num_ports = 15;
parameter g_num_ports = 6;
......@@ -259,8 +259,8 @@ scb_top_sim
.clk_startup_i ( clk_sys_i),
.clk_ref_i ( clk_ref_i),
.clk_dmtd_i ( clk_ref_i),
.clk_sys_i ( clk_sys_i),
.clk_swc_mpm_core_i ( clk_swc_mpm_core_i),
// .clk_sys_i ( clk_sys_i),
.clk_aux_i ( clk_swc_mpm_core_i),
.wb_adr_i ( cpu.master.adr),
.wb_dat_i ( cpu.master.dat_o),
.wb_dat_o ( cpu.master.dat_i),
......
testbench/swcore/swc_core_generic.sv
View file @ 747d1744
This diff is collapsed.
testbench/swcore/swc_param_defs.svh
View file @ 747d1744
......@@ -21,7 +21,7 @@
*
*/
////////////////////////////////////////////////////////////////
`define c_num_ports 16 //MAX: 16 //
`define c_num_ports 7 //MAX: 16 //
////////////////////////////////////////////////////////////////
`define c_prio_num 8 // c_swc_output_prio_num, [does not work, output block]
......@@ -30,7 +30,7 @@
`define c_mpm_mem_size 65536 //c_swc_packet_mem_size,
`define c_mpm_page_size 64 //c_swc_page_size,
`define c_mpm_ratio 2
`define c_mpm_ratio 4
`define c_mpm_fifo_size 4
`define c_mpm_fetch_next_pg_in_advance 0
......
top/bare_top/scb_top_bare.vhd
View file @ 747d1744
......@@ -111,7 +111,7 @@ entity scb_top_bare is
i2c_mbl0_sda_oen_o : out std_logic;
i2c_mbl0_sda_o : out std_logic;
i2c_mbl0_sda_i : in std_logic := '1'
);
);
end scb_top_bare;
architecture rtl of scb_top_bare is
......@@ -263,7 +263,7 @@ architecture rtl of scb_top_bare is
signal cyc_d0 : std_logic_vector(g_num_ports-1 downto 0);
signal pps_csync : std_logic;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
......@@ -283,17 +283,17 @@ begin
CS_ICON : chipscope_icon
port map (
CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
--CS_ICON : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
--CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
cnx_slave_in(0) <= cpu_wb_i;
......@@ -476,11 +476,12 @@ begin
phy_rx_enc_err_i => phys_i(i).rx_enc_err,
phy_rx_bitslide_i => phys_i(i).rx_bitslide,
txtsu_port_id_o => txtsu_timestamps(i).port_id(4 downto 0),
txtsu_frame_id_o => txtsu_timestamps(i).frame_id,
txtsu_tsval_o => txtsu_timestamps(i).tsval,
txtsu_valid_o => txtsu_timestamps(i).valid,
txtsu_ack_i => txtsu_timestamps_ack(i),
txtsu_port_id_o => txtsu_timestamps(i).port_id(4 downto 0),
txtsu_frame_id_o => txtsu_timestamps(i).frame_id,
txtsu_ts_value_o => txtsu_timestamps(i).tsval,
txtsu_ts_incorrect_o => txtsu_timestamps(i).incorrect,
txtsu_stb_o => txtsu_timestamps(i).stb,
txtsu_ack_i => txtsu_timestamps_ack(i),
rtu_full_i => rtu_full(i),
rtu_rq_strobe_p1_o => rtu_req(i).valid,
......@@ -536,7 +537,7 @@ begin
g_wb_ob_ignore_ack => false,
g_mpm_mem_size => 65536,
g_mpm_page_size => 64,
g_mpm_ratio => 8, --2
g_mpm_ratio => 4, --2
g_mpm_fifo_size => 8,
g_mpm_fetch_next_pg_in_advance => false)
port map (
......@@ -721,7 +722,7 @@ begin
gpio_out_o => gpio_o,
gpio_in_i => gpio_i);
U_MiniBackplane_I2C: xwb_i2c_master
U_MiniBackplane_I2C : xwb_i2c_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
......@@ -750,7 +751,7 @@ begin
-------------------------------------------------------------------------------
-- Various constant-driven I/Os
-------------------------------------------------------------------------------
clk_en_o <= '0';
clk_sel_o <= '0';
clk_sys_o <= clk_sys;
......
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