modules/wrsw_swcore: removed obsolete files

4e67ab38 · Tomasz Wlostowski · 05efcd1e · 05efcd1e · 05efcd1e · 05efcd1e
Commit 4e67ab38 authored Mar 26, 2012 by Tomasz Wlostowski
6 changed files
--- a/modules/wrsw_swcore/Makefile
+++ b/modules/wrsw_swcore/Makefile
-SRCS_VHDL = swc_swcore_pkg.vhd \
-swc_block_alloc.vhd \
-swc_core.vhd \
-swc_input_block.vhd \
-swc_lost_pck_dealloc.vhd \
-swc_multiport_linked_list.vhd \
-swc_multiport_page_allocator.vhd \
-swc_multiport_pck_pg_free_module.vhd \
-swc_ob_prio_queue.vhd \
-swc_output_block.vhd \
-swc_packet_mem.vhd \
-swc_packet_mem_read_pump.vhd \
-swc_packet_mem_write_pump.vhd \
-swc_page_alloc.vhd \
-swc_pck_pg_free_module.vhd \
-swc_pck_transfer_arbiter.vhd \
-swc_pck_transfer_input.vhd \
-swc_pck_transfer_output.vhd \
-swc_prio_encoder.vhd \
-swc_rr_arbiter.vhd 
-
-WORK = work
-
-#directories in which we should search for the VHDL/verilog source files
-VPATH =
-
-include ../../scripts/modules.mk
-
-
-
--- a/modules/wrsw_swcore/l0_init.mif
+++ b/modules/wrsw_swcore/l0_init.mif
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
-
-- Quartus II generated Memory Initialization File (.mif)
-
-WIDTH=32;
-DEPTH=32;
-
-ADDRESS_RADIX=UNS;
-DATA_RADIX=UNS;
-
-CONTENT BEGIN
-	[0..31]  :   4294967295;
-END;
--- a/modules/wrsw_swcore/swc_core_signle_port.vhd
+++ b/modules/wrsw_swcore/swc_core_signle_port.vhd
--- a/modules/wrsw_swcore/swc_packet_mem.vhd
+++ b/modules/wrsw_swcore/swc_packet_mem.vhd
--- a/modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
+++ b/modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
--- a/modules/wrsw_swcore/swc_packet_mem_write_pump.vhd
+++ b/modules/wrsw_swcore/swc_packet_mem_write_pump.vhd