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wr-switch-hdl
Commit 3a0bcd5b authored by li hongming's avatar li hongming
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Comment out "clk_sys_dbg_o" in ucf/top

parent b5af21d7
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top/scb_18ports/scb_top_synthesis.ucf
View file @ 3a0bcd5b
......@@ -14,7 +14,7 @@ NET "clk_ext_i" LOC=K13;
NET "clk_aux_p_o" LOC=B20;
NET "clk_aux_n_o" LOC=C19;
NET "clk_500_o" LOC=AM33;
NET "clk_sys_dbg_o" LOC=AL33;
# NET "clk_sys_dbg_o" LOC=AL33;
NET "ext_clk_62mhz_p_i" LOC = AN33;
NET "ext_clk_62mhz_n_i" LOC = AN34;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 3a0bcd5b
......@@ -78,7 +78,7 @@ entity scb_top_synthesis is
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
clk_sys_dbg_o: out std_logic;
-- clk_sys_dbg_o: out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......
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