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white-rabbit
wr-switch-hdl
Commits
00f3e992
Commit
00f3e992
authored
Feb 24, 2012
by
Maciej Lipinski
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scb_top_sythesis:bug fixing and making the swcore to synthesize
parent
1844c34e
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199 additions
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200 deletions
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-200
pll200MhZ.vhd
platform/xilinx/pll200MhZ.vhd
+1
-5
scb_top_synthesis.ucf
top/scb_18ports/scb_top_synthesis.ucf
+197
-195
scb_top_synthesis.vhd
top/scb_6ports/scb_top_synthesis.vhd
+1
-0
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platform/xilinx/pll200MhZ.vhd
View file @
00f3e992
...
...
@@ -113,12 +113,8 @@ begin
-- Input buffering
--------------------------------------
clkin1_buf
:
IBUFG
port
map
(
O
=>
clkin1
,
I
=>
CLK_IN1
);
CLKIN1
<=
clk_in1
;
-- Clocking primitive
--------------------------------------
...
...
top/scb_18ports/scb_top_synthesis.ucf
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00f3e992
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top/scb_6ports/scb_top_synthesis.vhd
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00f3e992
...
...
@@ -181,6 +181,7 @@ architecture Behavioral of scb_top_synthesis is
clk_dmtd_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_o
:
out
std_logic
;
clk_swc_mpm_core_i
:
in
std_logic
;
cpu_wb_i
:
in
t_wishbone_slave_in
;
cpu_wb_o
:
out
t_wishbone_slave_out
;
cpu_irq_n_o
:
out
std_logic
;
...
...
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