including sdb support, moving i2c to wrcore

e6a7b6c2 · Javier Díaz · f28764ae · e6a7b6c2 · e6a7b6c2 · e6a7b6c2
Commit e6a7b6c2 authored Jul 26, 2012 by Javier Díaz
19 changed files
--- a/doc/pdfs/wr-nic.pdf
+++ b/doc/pdfs/wr-nic.pdf
--- a/doc/wr-nic.mkd
+++ b/doc/wr-nic.mkd
@@ -9,12 +9,12 @@ This document focus on the description of the project gateware. This manual is p

 ![Basic wr-nic project elements](./img/wrnic_components.png)

-Note that the WR-NIC project inherits many code and working methodology of many other project. Specially important to highly the following ones: 
+Note that the WR-NIC project inherits many code and working methodology of many other projects. Specially important to highly the following ones: 

-1. White-Rabbit core collection: http://www.ohwr.org/projects/wr-cores (wishbonized branch). Look at the WR PTP Core. It is a black-box standalone WR-PTP protocol core, incorporating a CPU, WR MAC and PLLs. It is also convenient to look at TxTSU and NIC project. For further details, search for its related wbgen2 files (extension .wb). 
-2. Software for White-Rabbit PTP core: http://www.ohwr.org/projects/wrpc-sw (a subproject of the previous one)
-3. Gennum GN4124 core: http://www.ohwr.org/projects/gn4124-core 
-4. The platform independent core collection: http://www.ohwr.org/projects/general-cores. An important one is the Wishbone crossbar with is download at the DOWNLOAD_PATH/wr-cores/ip_cores/general-cores/modules/wishbone. 
+1. White-Rabbit core collection: `http://www.ohwr.org/projects/wr-cores` (wishbonized branch). Look at the WR PTP Core. It is a black-box standalone WR-PTP protocol core, incorporating a CPU, WR MAC and PLLs. It is also convenient to look at TxTSU and NIC project. For further details, search for its related wbgen2 files (extension .wb). 
+2. Software for White-Rabbit PTP core: `http://www.ohwr.org/projects/wrpc-sw` (a subproject of the previous one)
+3. Gennum GN4124 core: `http://www.ohwr.org/projects/gn4124-core` 
+4. The platform independent core collection: `http://www.ohwr.org/projects/general-cores`. An important one is the Wishbone crossbar with is download at the DOWNLOAD_PATH/wr-cores/ip_cores/general-cores/modules/wishbone. 

 Gateware elements
 =====================
@@ -29,20 +29,43 @@ Here is a quick description of each block:
 * The `WB intercon` block ensures seamless interconnection of Wishbone masters and slaves using a crossbar topology.
 The `GN4124 core` is a bridge between the GN4124 PCIe interface chip and the internal Wishbone bus, allowing communication with the host and interrupts --> pipelined version!
 * The `WRPC (White Rabbit PTP Core)` communicates with the outside world through the SFP socket in the SPEC, typically using fiber optics. It deals with the WR PTP using an internal LM32 CPU running a portable PTP stack. It forwards/receives non-PTP frames to/from the NIC block, using two pipelined Wishbone interfaces (master and slave for forwarding and receiving respectively). It also provides time information to other cores (not represented in the diagram), and time-tags for transmitted and received frames that can be read through Wishbone for diagnostics purposes. Future versions will include the PPSi library instead of the current PTP stack. 
-* The `NIC core` ensures communication between the host and the WRPC. More precisely, it interrupts the host and provides a descriptor that the host can use to fetch incoming frames. For outgoing frames, it receives a descriptor from the host, fetches the frame using PCIe DMA via the GN4124 core and sends it to the WRPC using a pipelined Wishbone interface.
-* The `TxTSU module` collect timestamps with associated frame identifiers and puts them in a shared FIFO (port identifier is also included although not required for the SPEC card because only one Ethernet port is available). A IRQ is triggered when FIFO is not empty so drivers could read TX timestamps and frame/port identifiers. 
+* The `NIC core` ensures communication between the host and the WRPC. More precisely, it interrupts the host and provides a descriptor that the host can use to fetch incoming frames. For outgoing frames, it receives a descriptor from the host, fetches the frame using PCIe via the GN4124 core and sends it to the WRPC using a pipelined Wishbone interface.
+* The `TxTSU module` collect timestamps with associated Ethernet frame identifiers and puts them in a shared FIFO (port identifier is also included although not required for the SPEC card because only one Ethernet port is available but it is include to provide a common descriptor with the switch data). A IRQ is triggered when FIFO is not empty so drivers could read TX timestamps and frame/port identifiers. 

+In the next sections we provide a little more information about `DIO core` and the `WRPC (White Rabbit PTP Core)` in order to understand better how the whole system works. 
+
+WRPC (White Rabbit PTP Core)
+----------------------------
+The `WRPC (White Rabbit PTP Core)` block is the HDL block that makes possible the White-Rabbit timing functionalities on the White-Rabbit nodes. It is a black-box standalone WR-PTP protocol core, incorporating a CPU LM32, WR MAC and PLLs. It could be configure to work on 3 different operations modes:  
+
+* Grandmaster: WRPC locks to a external 10 MHz and PPS signal provided for instance from a Cesium clock / GPS. This signals are provided from the channel 4 (PPS) and channel 5 (10 MHz) lemo connectors of the DIO card.
+
+* Master: the systems uses the VCO oscillators of the SPEC board basically on a free running modes. 
+
+* Slaves: The clock information is recovered from the Ethernet connections and the local clock uses the DDMTD method to follow the external clock.  
+
+In this project, WRPC provides the timing information used for accurate output generation and input time stamping of the DIO signals. Note that this data is provided with an accuracy of 8 ns. 
+
+It is important to remark that for this release the I2C bus of the FMC-DIO card is connected to WRPC. This is needed because current implementation of WRPC store configuration data on the FMC-DIO card EEPROM. Please be aware that for future releases this could change. 
+ 
+The whole description of the core goes beyond the scope of this documentation but the additional information is available at: `http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core` and in: 
+
+G. Daniluk, White Rabbit PTP Core the sub-nanosecond time synchronization over Ethernet, 2012.
+M.Sc thesis describing the development and implementation of the first standalone HDL module handling the sub-nanosecond synchronization over a regular Ethernet - the White Rabbit PTP Core.
+Available at: `http://www.ohwr.org/attachments/1368/GD_mgr.pdf` 

 DIO core
 ----------
-The `DIO Core` block is the HDL block that access to the fmc-dio-5chls mezzanine card. Their main elements are shown on the next figure. 
+The `DIO Core` block is the HDL block that access to the fmc-dio-5chls mezzanine card. The core goes beyond a standard GPIO core to include advanced functionalities related with timing. Their main elements are shown on the next figure. 

 ![Main DIO Core block elements](./img/diocore2.png)

 The different submodules description are:  

 * `GPIO:` It allows to enable/disable the output drivers and the termination resistors.
-* `I2C:` It allows to set the threshold of the ADCMP604 fast LVDS comparator and to access to write/read data to the EEPROM memory (24AA64).
+
+* `I2C:` It allows to set the threshold of the ADCMP604 fast LVDS comparator and to access to write/read data to the EEPROM memory (24AA64). Please note that already commented, current release do not allow to access I2C signals of the FMC-DIO card from this HDL block. This is assigned to WRPC and therefore it should be handled inside its memory maps (concretely, inside WRPC `Syscon` device). This could change for future releases.
+
 * `Onewire:` It is used for temperature acquisition

 * Modules to generate or stamping pulses:  
@@ -57,9 +80,7 @@ The different submodules description are:
 	3. Interrupt control registers that allow to configure the interrupts  generated when there are data in the FIFOs.
 	4. Monostable register, which generates a single clock cycle-long

-
-
-Configuration & Control
+DIO Configuration & Control
 ==========================
 Accessing to the different system elements is as simple as doing a read/write memory access. The memory map of the different elements of the board are: 


--- a/modules/wrsw_dio/Manifest.py
+++ b/modules/wrsw_dio/Manifest.py
 files = ["wrsw_dio_wb.vhd",
 	      "xwrsw_dio.vhd",
+              "wrsw_dio.vhd",
+              "wrnic_sdb_pkg.vhd",
 	      "pulse_gen_pl.vhd",
-         "immed_pulse_counter.vhd",	
+              "immed_pulse_counter.vhd",	
 	      "dummy_time.vhd" ]

--- a/modules/wrsw_dio/wrnic_sdb_pkg.vhd
+++ b/modules/wrsw_dio/wrnic_sdb_pkg.vhd
--- a/modules/wrsw_dio/wrsw_dio.vhd
+++ b/modules/wrsw_dio/wrsw_dio.vhd
--- a/modules/wrsw_dio/xwrsw_dio.vhd
+++ b/modules/wrsw_dio/xwrsw_dio.vhd
@@ -2,7 +2,7 @@
 -- Title      : DIO Core
 -- Project    : White Rabbit Network Interface
 -------------------------------------------------------------------------------
-- File       : wrsw_dio.vhd
+-- File       : xwrsw_dio.vhd
 -- Author     : Rafael Rodriguez, Javier Díaz
 -- Company    : Seven Solutions
 -- Created    : 2012-03-03
@@ -17,13 +17,14 @@
 -- to schedule the generation of a pulse at a given future seconds time, or to generate 
 -- it immediately. 
 -------------------------------------------------------------------------------
-- TODO:
+-- TODO: Include wb adapter
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
 -- 2012-03-03  0.1      Rafa.r          Created
-- 2012-03-08  0.2      Javier.d        Added wrsw_dio_wb
-- 2012-07-05  0.3		Javier.d        Midified wrsw_dio_wb, modified interface
+-- 2012-03-08  0.1      JDiaz           Added wrsw_dio_wb
+-- 2012-07-05  0.2		JDiaz           Modified wrsw_dio_wb, modified interface
+-- 2012-07-20  0.2		JDiaz           Include sdb support
 -------------------------------------------------------------------------------
 --     Memory map:
 --       0x000: DIO-ONEWIRE
@@ -38,7 +39,7 @@ use ieee.numeric_std.all;

 library work;
 use work.wishbone_pkg.all;
-
+use work.wrnic_sdb_pkg.all;

 entity xwrsw_dio is
  generic (
@@ -68,16 +69,15 @@ entity xwrsw_dio is
    tm_time_valid_i  : in std_logic;
    tm_seconds_i         : in std_logic_vector(39 downto 0);
    tm_cycles_i      : in std_logic_vector(27 downto 0);
-
-    -- Debug signals for chipscope
+		
+    slave_i            : in  t_wishbone_slave_in;
+    slave_o            : out t_wishbone_slave_out;
+   
+	-- Debug signals for chipscope
    TRIG0            : out std_logic_vector(31 downto 0);
    TRIG1            : out std_logic_vector(31 downto 0);
    TRIG2            : out std_logic_vector(31 downto 0);
-    TRIG3            : out std_logic_vector(31 downto 0);
-		
-    slave_i            : in  t_wishbone_slave_in;
-    slave_o            : out t_wishbone_slave_out
-  --  wb_irq_data_fifo_o : out std_logic  -- T.B.DELETED
+    TRIG3            : out std_logic_vector(31 downto 0)	 	 	 
  );
  end xwrsw_dio; 

@@ -375,18 +375,14 @@ architecture rtl of xwrsw_dio is
  signal tm_seconds             : std_logic_vector (39 downto 0);
  signal tm_cycles              : std_logic_vector (27 downto 0);
 	
-  -- WB Crossbar
-  constant c_cfg_base_addr : t_wishbone_address_array(3 downto 0) :=
-    (0 => x"00000000",  -- ONEWIRE                
-     1 => x"00000100",  -- I2C                
-     2 => x"00000200",  -- GPIO                 
-     3 => x"00000300"); -- PULSE GEN & STAMPER                 
-
-  constant c_cfg_base_mask : t_wishbone_address_array(3 downto 0) :=
-    (0 => x"00000f00",
-     1 => x"00000f00",
-     2 => x"00000f00",
-     3 => x"00000f00");
+  -- WB SDB Crossbar
+  constant c_diobar_layout : t_sdb_record_array(3 downto 0) :=
+    (0 => f_sdb_embed_device(c_xwb_onewire_master_sdb ,   x"00000000"), -- ONEWIRE
+     1 => f_sdb_embed_device(c_xwb_i2c_master_sdb     ,   x"00000100"), -- I2C
+     2 => f_sdb_embed_device(c_xwb_gpio_port_sdb      ,   x"00000200"), -- GPIO
+     3 => f_sdb_embed_device(c_xwrsw_dio_wb_sdb       ,   x"00000300")  -- DIO REGISTERS
+     );	  
+  constant c_diobar_sdb_address : t_wishbone_address := x"00000400";	  

  signal cbar_master_in   : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
  signal cbar_master_out  : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
@@ -444,7 +440,7 @@ begin
 		  );
 	 

-    U_pulse_stamper : pulse_stamper
+    U_PULSE_STAMPER : pulse_stamper
      port map(
        clk_ref_i       => clk_ref_i,
        clk_sys_i       => clk_sys_i,
@@ -469,10 +465,10 @@ begin
  ------------------------------------------------------------------------------
  -- WB ONEWIRE MASTER
  ------------------------------------------------------------------------------    
-  U_Onewire : xwb_onewire_master
+  U_ONEWIRE : xwb_onewire_master
    generic map (
      g_interface_mode => PIPELINED,
-      g_address_granularity => BYTE,
+      g_address_granularity => g_address_granularity,
      g_num_ports      => 1)
    port map (
      clk_sys_i        => clk_sys_i,
@@ -492,7 +488,7 @@ begin
  U_I2C : xwb_i2c_master
    generic map (
      g_interface_mode => PIPELINED,
-      g_address_granularity => BYTE
+      g_address_granularity => g_address_granularity
      )
    
    port map (
@@ -522,7 +518,7 @@ begin
  U_GPIO : xwb_gpio_port
    generic map (
      g_interface_mode         => PIPELINED,
-      g_address_granularity => BYTE,
+      g_address_granularity => g_address_granularity,
      g_num_pins               => 32,
      g_with_builtin_tristates => false)
    port map (
@@ -539,26 +535,26 @@ begin
  ------------------------------------------------------------------------------
  -- WB Crossbar
  ------------------------------------------------------------------------------
-  WB_INTERCON : xwb_crossbar
+ WB_DIO_INTERCON : xwb_sdb_crossbar
    generic map(
      g_num_masters => 1,
      g_num_slaves  => 4,
      g_registered  => true,
-      -- Address of the slaves connected
-      g_address     => c_cfg_base_addr,
-      g_mask        => c_cfg_base_mask
+      g_wraparound  => true,
+      g_layout      => c_diobar_layout,
+      g_sdb_addr    => c_diobar_sdb_address
      )
    port map(
-      clk_sys_i     => clk_sys_i,
-      rst_n_i       => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
      -- Master connections
      slave_i(0)    => slave_bypass_i,
      slave_o(0)    => slave_bypass_o,
      -- Slave conenctions
      master_i      => cbar_master_in,
      master_o      => cbar_master_out
-      );
-	
+      );				
+
  -- Irq form one slave is bypassed to the Master connection 
  slave_bypass_i.cyc <= slave_i.cyc;
  slave_bypass_i.stb <= slave_i.stb;
@@ -604,9 +600,9 @@ begin
  dio_sdn_n_o    <= gpio_out(31);
  
  ------------------------------------------------------------------------------
-  -- WB seconds-BASED PULSE GENERATION & INPUT STAMPING
+  -- WB DIO control registers
  ------------------------------------------------------------------------------  
-  U_seconds_wbslave : wrsw_dio_wb 
+  U_DIO_REGISTERS : wrsw_dio_wb 
    port map(
      rst_n_i     => rst_n_i,
      clk_sys_i   => clk_sys_i,

--- a/syn/spec/wr_nic.xise
+++ b/syn/spec/wr_nic.xise
--- a/testbench/top_level/Manifest.py
+++ b/testbench/top_level/Manifest.py
@@ -4,5 +4,5 @@ vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"

 files = [ "main.sv" ]

-modules = { "local" :  [ "../..", "../../top/spec", "gn4124_bfm"] }
+modules = { "local" :  [ "../..", "../../top/spec", "./gn4124_bfm"] }

--- a/testbench/top_level/main.sv
+++ b/testbench/top_level/main.sv
@@ -3,10 +3,11 @@
 `include "gn4124_bfm.svh"   

 const uint64_t BASE_WRPC = 'h0080000;
-const uint64_t BASE_NIC = 'ha0000;
-const uint64_t BASE_VIC = 'hc0000;
-const uint64_t BASE_TXTSU = 'h000d0000;
-const uint64_t BASE_DIO = 'h000e0000;
+const uint64_t BASE_NIC =  'h00c0000;
+const uint64_t BASE_VIC =  'h00e0000;
+const uint64_t BASE_TXTSU ='h00e1000;
+const uint64_t BASE_DIO =  'h00e2000;
+

 module main;
   reg clk_125m_pllref = 0;
@@ -17,7 +18,7 @@ module main;
   
   IGN4124PCIMaster I_Gennum ();

-   wr_nic_top
+   wr_nic_sdb_top
     DUT (
          .clk_125m_pllref_p_i(clk_125m_pllref),
          .clk_125m_pllref_n_i(~clk_125m_pllref),
@@ -35,7 +36,7 @@ module main;

      $display("Startup");

-      acc.write('ha0400, 'h1deadbee);
+      acc.write('ha0400, 'h1deadbee); // reset lm32, h20004
      acc.write('ha0400, 'h0deadbee);      

      acc.write('hc0000, 'h0deadbee);      
@@ -52,7 +53,7 @@ module main;
      acc.read(BASE_WRPC + 'h100, rval);
      $display("MemReadback1 %x", rval);
      acc.read(BASE_WRPC + 'h104, rval);
-      $display("MemReadback2 %x", rval);
+      //$display("MemReadback2 %x", rval);

 /* -----\/----- EXCLUDED -----\/-----
      acc.write(BASE_VIC + 'h4, 'h1); // enable IRQ 0

--- a/testbench/wrsw_dio/Manifest.py
+++ b/testbench/wrsw_dio/Manifest.py
+action = "simulation"
+target = "xilinx"
+fetchto = "../../ip_cores"
+vlog_opt="+incdir+../../sim"
+
+files = [ "main.sv" ]
+
+modules = { "local" :  "../.." }
+
--- a/testbench/wrsw_dio/main.sv
+++ b/testbench/wrsw_dio/main.sv
+`timescale 1ns/1ps
+
+`include "tbi_utils.sv"
+   
+`include "simdrv_defs.svh"
+`include "if_wb_master.svh"
+
+module main;
+
+   wire clk_ref;
+   wire clk_sys;
+   wire rst_n;
+
+   wire clk_sys_dly;
+   wire time_valid;
+
+   IWishboneMaster WB (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)); 
+   
+  tbi_clock_rst_gen
+     #(
+       .g_rbclk_period(8000))  
+  clkgen( 
+	.clk_ref_o(clk_ref),
+	.clk_sys_o(clk_sys),
+	.rst_n_o(rst_n));
+
+
+   assign  #10 clk_sys_dly  = clk_sys;
+   assign  #1  time_valid =1'b1;
+  
+   wrsw_dio 
+      #(
+        .g_interface_mode(PIPELINED),
+        .g_address_granularity(BYTE)) 
+    DUT(
+      .clk_sys_i (clk_sys),
+      .clk_ref_i (clk_ref),
+      .rst_n_i   (rst_n),
+
+      .tm_time_valid_i(time_valid),
+
+      .wb_cyc_i  (WB.master.cyc),
+      .wb_stb_i  (WB.master.stb),
+      .wb_we_i   (WB.master.we),
+      .wb_sel_i  (4'b1111),
+      .wb_adr_i  (WB.master.adr[31:0]),
+      .wb_dat_i  (WB.master.dat_o),
+      .wb_dat_o  (WB.master.dat_i),
+      .wb_ack_o  (WB.master.ack),
+      .wb_stall_o(WB.master.stall)
+    );
+
+
+   initial begin
+      CWishboneAccessor acc;
+      uint64_t data;
+
+      @(posedge rst_n);
+      repeat(3) @(posedge clk_sys);
+
+      #1us;
+            
+      acc  = WB.get_accessor();
+      acc.set_mode(PIPELINED);
+      
+     #1us;
+      acc.write(32'h00000000, 'hdeadbeef);
+      //acc.write(32'h00008000, 'hdeadbeef);
+
+      //#1us;
+      acc.write(32'h00000004, 'hcafebabe);
+      //acc.write(32'h00008004, 'hcafebabe);
+
+ /*     acc.read(32'h00000000, data);
+      acc.read(32'h00000004, data);
+      //acc.read(32'h00008000, data);
+      //acc.read(32'h00008004, data);
+
+      acc.write(32'h0000004c, 'habcdef00);
+      acc.read(32'h00000004c, data);     */
+      
+   end
+   
+   
+endmodule // main
+
--- a/testbench/wrsw_dio/run.do
+++ b/testbench/wrsw_dio/run.do
+vlog -sv main.sv +incdir+"." +incdir+../../sim
+make -f Makefile
+vsim -L unisim -t 10fs work.main -voptargs="+acc"
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 25us
+wave zoomfull
+radix -hexadecimal
--- a/testbench/wrsw_dio/wave.do
+++ b/testbench/wrsw_dio/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/clk_sys_i
+add wave -noupdate /main/DUT/clk_ref_i
+add wave -noupdate /main/DUT/rst_n_i
+add wave -noupdate /main/DUT/tm_time_valid_i
+
+add wave -divider WB
+add wave -noupdate /main/DUT/wb_cyc_i
+add wave -noupdate /main/DUT/wb_stb_i
+add wave -noupdate /main/DUT/wb_we_i
+add wave -noupdate /main/DUT/wb_sel_i
+add wave -noupdate /main/DUT/wb_adr_i
+add wave -noupdate /main/DUT/wb_dat_i
+add wave -noupdate /main/DUT/wb_dat_o
+add wave -noupdate /main/DUT/wb_ack_o
+add wave -noupdate /main/DUT/wb_stall_o
+
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {90556826170 fs} {90813173830 fs}
--- a/testbench/wrsw_nic/Manifest.py
+++ b/testbench/wrsw_nic/Manifest.py
 action = "simulation"
+target = "xilinx"
 fetchto = "../../ip_cores"
 vlog_opt="+incdir+../../sim"


--- a/testbench/wrsw_nic/main.sv
+++ b/testbench/wrsw_nic/main.sv
@@ -14,6 +14,7 @@ module main;
   IWishboneMaster WB (
      .clk_i(clk_sys),
      .rst_n_i(rst_n)); 
+   
   tbi_clock_rst_gen
     #(
       .g_rbclk_period(8000))
@@ -27,24 +28,22 @@ module main;

   assign  #10 clk_sys_dly  = clk_sys;
  
-    wrsw_nic #(
-      .g_USE_DMA    (1)
-    )
+    wrsw_nic 
    DUT (
-	    .clk_sys_i      (clk_sys),
-    	.rst_n_i        (rst_n),
-
-      //.wb_cyc_i  (WB.master.cyc),
-      //.wb_stb_i  (WB.master.stb),
-      //.wb_we_i   (WB.master.we),
-      //.wb_sel_i  (4'b1111),
-      //.wb_adr_i  (WB.master.adr[31:0]),
-      //.wb_dat_i  (WB.master.dat_o),
-      //.wb_dat_o  (WB.master.dat_i),
-      //.wb_ack_o  (WB.master.ack),
-      //.wb_stall_o(WB.master.stall)
-
-      .dma_cyc_i  (WB.master.cyc),
+      .clk_sys_i (clk_sys),
+      .rst_n_i   (rst_n),
+
+      .wb_cyc_i  (WB.master.cyc),
+      .wb_stb_i  (WB.master.stb),
+      .wb_we_i   (WB.master.we),
+      .wb_sel_i  (4'b1111),
+      .wb_adr_i  (WB.master.adr[31:0]),
+      .wb_dat_i  (WB.master.dat_o),
+      .wb_dat_o  (WB.master.dat_i),
+      .wb_ack_o  (WB.master.ack),
+      .wb_stall_o(WB.master.stall)
+
+      /*.dma_cyc_i  (WB.master.cyc),
      .dma_stb_i  (WB.master.stb),
      .dma_we_i   (WB.master.we),
      .dma_sel_i  (4'b1111),
@@ -52,7 +51,7 @@ module main;
      .dma_dat_i  (WB.master.dat_o),
      .dma_dat_o  (WB.master.dat_i),
      .dma_ack_o  (WB.master.ack),
-      .dma_stall_o(WB.master.stall)
+      .dma_stall_o(WB.master.stall)*/
    );


@@ -82,8 +81,8 @@ module main;
      //acc.read(32'h00008000, data);
      //acc.read(32'h00008004, data);

-
-      
+      acc.write(32'h0000004c, 'habcdef00);
+      acc.read(32'h00000004c, data);     
      
   end
   

--- a/testbench/wrsw_nic/wave.do
+++ b/testbench/wrsw_nic/wave.do
 onerror {resume}
 quietly WaveActivateNextPane {} 0
-add wave -noupdate /main/DUT/g_USE_DMA
+#add wave -noupdate /main/DUT/g_USE_DMA
 add wave -noupdate /main/DUT/clk_sys_i
 add wave -noupdate /main/DUT/rst_n_i

-add wave -divider DMA
-add wave -noupdate /main/DUT/dma_cyc_i
-add wave -noupdate /main/DUT/dma_stb_i
-add wave -noupdate /main/DUT/dma_we_i
-add wave -noupdate /main/DUT/dma_sel_i
-add wave -noupdate /main/DUT/dma_adr_i
-add wave -noupdate /main/DUT/dma_dat_i
-add wave -noupdate /main/DUT/dma_dat_o
-add wave -noupdate /main/DUT/dma_ack_o
-add wave -noupdate /main/DUT/dma_stall_o
+#add wave -divider DMA
+#add wave -noupdate /main/DUT/dma_cyc_i
+#add wave -noupdate /main/DUT/dma_stb_i
+#add wave -noupdate /main/DUT/dma_we_i
+#add wave -noupdate /main/DUT/dma_sel_i
+#add wave -noupdate /main/DUT/dma_adr_i
+#add wave -noupdate /main/DUT/dma_dat_i
+#add wave -noupdate /main/DUT/dma_dat_o
+#add wave -noupdate /main/DUT/dma_ack_o
+#add wave -noupdate /main/DUT/dma_stall_o

 add wave -divider WB
 add wave -noupdate /main/DUT/wb_cyc_i
@@ -35,8 +35,8 @@ add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_data_i
 add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/wb_data_o

 add wave -divider BRAM
-add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/RAM/ram(0:5)
-
+add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/RAM/qb_o 
+#add wave -noupdate /main/DUT/U_Wrapped_NIC/U_BUFFER/RAM/ram(0:5)

 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}

--- a/top/spec/Manifest.py
+++ b/top/spec/Manifest.py
-files = ["wr_nic_top.vhd", "wr_nic_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd" ]
+files = ["wr_nic_sdb_top.vhd", "wr_nic_sdb_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd" ]

 fetchto = "../../ip_cores"

 modules = {
-					 "local" : ["../../"]
-					}
+	   "local" : ["../../"]
+	}
--- a/top/spec/wr_nic_sdb_top.ucf
+++ b/top/spec/wr_nic_sdb_top.ucf
--- a/top/spec/wr_nic_sdb_top.vhd
+++ b/top/spec/wr_nic_sdb_top.vhd