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wr-nic
Commit dbff4e85 authored by Rafael Rodriguez's avatar Rafael Rodriguez
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added functionality: to generate pulses immediately

parent 04cd718b
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modules/wrsw_dio/wrsw_dio.vhd
View file @ dbff4e85
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modules/wrsw_dio/wrsw_dio.wb
View file @ dbff4e85
......@@ -535,4 +535,48 @@ peripheral {
};
-- Pulse generator.
reg {
name = "Pulse generate immediately";
description = "It is used to generate a pulse immediately";
prefix = "puls_inmed";
field {
name = "pulse_gen_now_0";
description = "It generates a pulse";
prefix = "pul_inm_0";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_1";
description = "It generates a pulse";
prefix = "pul_inm_1";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_2";
description = "It generates a pulse";
prefix = "pul_inm_2";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_3";
description = "It generates a pulse";
prefix = "pul_inm_3";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_4";
description = "It generates a pulse";
prefix = "pul_inm_4";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
};
};
modules/wrsw_dio/wrsw_dio_wb.htm 100755 → 100644
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modules/wrsw_dio/wrsw_dio_wb.vhd 100755 → 100644
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software_test_dio_core/test_pulse.py
View file @ dbff4e85
......@@ -32,42 +32,45 @@ def main(default_directory="."):
print
print "(------------CONFIGURING DIO CHANNELS--------------)"
print "Value of LEMOs with all drivers enabled and terminations disabled",
print "Value of LEMOs with all drivers enabled and terminations disabled"
for lemon in range(5):
dio.set_term(lemon, 0)
dio.set_dir(lemon, 1)
dio.set_in_threshold(lemon,30)
dio.set_in_threshold(lemon,15)
print "Input threshold set to an intermediate level ({}).".format(dio.get_in_threshold(0))
print
print "(------------CONFIGURING INTERRUPTS--------------)"
print "(DIO Interrupts)"
# DIO Interrupts
dio.set_reg(0x64, 0x1f) # Interrupts when the fifos have datas (UTC time from the pulse stamper)
mask_irq = dio.get_reg(0x68)
print "mask_irq =>", mask_irq
print "MASK IRQ DIO =>", mask_irq
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ =>", status_irq
print "STATUS IRQ DIO =>", status_irq
# DIO Interrupts
# VIC Interrupts
print "(VIC Interrupts)"
VIC = VIC_irq(spec, 0x40000)
VIC.set_reg(0x0, 0x3) # control register
control_irq_vic = VIC.get_reg(0x0)
print "control_irq_vic =>", control_irq_vic
VIC.set_reg(0x8, 0x3) # enable register
print "CONTROL IRQ VIC =>", control_irq_vic
VIC.set_reg(0x8, 0x7) # enable register
mask_irq_vic = VIC.get_reg(0x10)
print "mask_irq_vic =>", mask_irq_vic
print "MASK IRQ VIC =>", mask_irq_vic
#VIC.set_reg(0x18, 0x7) # generate soft irq
print
print "(------------CONFIGURING TRIG UTC TIME FOR EACH LEMO--------------)"
print "Note: The dummy time core is already running after configuring the fpga"
print "Note: The dummy time core is already running after configuring the fpga, therefore you should run this program"
print "before the configured trigger time below."
dio_rdy = dio.get_reg(0x40)
# if dio_rdy != 0x1f:
# print "Some pulse_gen module isn't ready to accept next trigger time tag, dio_rdy:", dio_rdy
# exit()
if dio_rdy != 0x1f:
print "Some pulse_gen module isn't ready to accept next trigger time tag, dio_rdy:", dio_rdy
exit()
#TIME TRIGGERS
dio.set_reg(0x0, 20) #trig0 UTC_low
dio.set_reg(0x4, 0) #trig0 UTC_high
dio.set_reg(0x8, 0) #trig0 cycles
......@@ -90,79 +93,65 @@ def main(default_directory="."):
dio.set_reg(0x3c, 0x1f) #all trigX Enabled
print
print "Waiting pulse stamper from DIO 0...."
status_fifo_reg_0 = dio.get_reg(0x7c)
while(status_fifo_reg_0 != 0x1): #counter = 0x1
status_fifo_reg_0 = dio.get_reg(0x7c)
time = dio.get_reg_long(0x70)
cycles = dio.get_reg_long(0x78)
print "UTC DIO 0 =>", time
print "cycles DIO 0 =>", cycles
print
print
print "Waiting pulse stamper from DIO 1...."
status_fifo_reg_0 = dio.get_reg(0x8c)
while(status_fifo_reg_0 != 0x1): #counter = 0x1
status_fifo_reg_0 = dio.get_reg(0x8c)
time = dio.get_reg_long(0x80)
cycles = dio.get_reg_long(0x88)
print "UTC DIO 1 =>", time
print "cycles DIO 1 =>", cycles
print
adr_status_fifo = [0x7c, 0x8c, 0x9c, 0xac, 0xbc]
adr_time = [0x70, 0x80, 0x90, 0xa0, 0xb0]
adr_cycles = [0x78, 0x88, 0x98, 0xa8, 0xb8]
for dio_pulse in range(5):
print "Waiting pulse stamper from DIO ", dio_pulse," ...."
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
while((status_fifo_reg & 0xff) != 0x1): #counter = 0x1
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
time = dio.get_reg_long(adr_time[dio_pulse])
cycles = dio.get_reg(adr_cycles[dio_pulse])
print "UTC DIO dio_pulse =>", time
print "cycles DIO dio_pulse =>", cycles
print
status_irq_vic = VIC.get_reg(0x4)
print "STATUS VIC IRQ =>", status_irq_vic
print
print "Waiting pulse stamper from DIO 2...."
status_fifo_reg_0 = dio.get_reg(0x9c)
while(status_fifo_reg_0 != 0x1): #counter = 0x1
status_fifo_reg_0 = dio.get_reg(0x9c)
time = dio.get_reg_long(0x90)
cycles = dio.get_reg_long(0x98)
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ DIO =>", status_irq
print "UTC DIO 2 =>", time
print "cycles DIO 2 =>", cycles
print
print "(-----------IMMEDIATE PULSE GENERATION (5 pulses for each DIO)---------------)"
for num_pulses in range(5):
dio.set_reg(0x44, 0x1f) # To generate 5 pulses for each DIO
print
print "Waiting pulse stamper from DIO 3...."
status_fifo_reg_0 = dio.get_reg(0xac)
while(status_fifo_reg_0 != 0x1): #counter = 0x1
status_fifo_reg_0 = dio.get_reg(0xac)
time = dio.get_reg_long(0xa0)
cycles = dio.get_reg_long(0xa8)
status_irq_vic = VIC.get_reg(0x4)
print "STATUS VIC IRQ =>", status_irq_vic
print "UTC DIO 3 =>", time
print "cycles DIO 3 =>", cycles
print
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ DIO =>", status_irq
print
print "Waiting pulse stamper from DIO 4...."
status_fifo_reg_0 = dio.get_reg(0xbc)
while(status_fifo_reg_0 != 0x1): #counter = 0x1
status_fifo_reg_0 = dio.get_reg(0xbc)
for dio_pulse in range(5): # reading of pulses
print "------Pulses from DIO ", dio_pulse, ":"
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
cont = 0
while((status_fifo_reg & 0xff) != 0x0):
time = dio.get_reg_long(adr_time[dio_pulse])
cycles = dio.get_reg(adr_cycles[dio_pulse])
print "Pulse ", cont
print "UTC DIO dio_pulse =>", time
print "cycles DIO dio_pulse =>", cycles
status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
cont = cont + 1
print
time = dio.get_reg_long(0xb0)
cycles = dio.get_reg_long(0xb8)
print "UTC DIO 4 =>", time
print "cycles DIO 4 =>", cycles
print
status_irq_vic = dio.get_reg(0x4)
status_irq_vic = VIC.get_reg(0x4)
print "STATUS VIC IRQ =>", status_irq_vic
status_irq = dio.get_reg(0x6c)
print "STATUS IRQ DIO =>", status_irq
# print "Waiting irq ..."
# gennum.wait_irq()
......
top/spec/wr_nic_top.vhd
View file @ dbff4e85
......@@ -810,7 +810,9 @@ begin
cfg_mask_i => c_cfg_base_mask
);
------------------------------------------------------------------------------
-- Gennun Core
------------------------------------------------------------------------------
U_Gennum_Core: gn4124_core
port map (
rst_n_a_i => L_RST_N,
......@@ -863,12 +865,10 @@ begin
end if;
end process;
-- cbar_slave_i.adr(1 downto 0) <= (others => '0');
-- cbar_slave_i.adr(31 downto 19) <= (others => '0');
fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
fpga_sda_b <= '0' when wrc_sda_o = '0' else 'Z';
wrc_scl_i <= fpga_scl_b;
wrc_sda_i <= fpga_sda_b;
fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
fpga_sda_b <= '0' when wrc_sda_o = '0' else 'Z';
wrc_scl_i <= fpga_scl_b;
wrc_sda_i <= fpga_sda_b;
sfp_mod_def1_b <= '0' when sfp_scl_o = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_o = '0' else 'Z';
......@@ -956,7 +956,7 @@ begin
tm_cycles_o => tm_cycles,
pps_p_o => pps,
dio_o => open, --dio_out(4 downto 1),
dio_o => open,
rst_aux_n_o => open
);
......@@ -1027,7 +1027,7 @@ begin
vic_slave_irq(0) <= cbar_master_i(3).int; -- wrpc, txtsu
vic_slave_irq(1) <= cbar_master_i(1).int; -- wrsw-nic
vic_slave_irq(2) <= cbar_master_i(4).int; -- DIO core
vic_slave_irq(2) <= wb_irq_data_fifo_dio; -- DIO core
-------------------------------------
-- WRSW TXTSU
......@@ -1220,7 +1220,7 @@ begin
-- port map (
-- CONTROL0 => CONTROL
-- );
--
-- TRIG2(5 downto 0) <= GPIO(0) & wb_irq_data_fifo_dio & vic_irq & vic_slave_irq;
--
-- TRIG0 <= cbar_master_o(4).adr(19 downto 0) & cbar_master_o(4).dat(7 downto 0) &
......@@ -1230,7 +1230,7 @@ begin
--
-- TRIG1 <= cbar_slave_i.adr(19 downto 0) & cbar_slave_o.dat(7 downto 0) &
-- cbar_slave_i.cyc & cbar_slave_i.stb & cbar_slave_i.we & cbar_slave_o.ack;
--
end rtl;
......
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