Commit 7c275f64 authored by Benoit Rat's avatar Benoit Rat

dio: add P/p & C/c mode to DIO.

Create the a new inout register to setup default value.
use it instead of GPIO register for O_E_N and TERM_E.
parent 0bdc4413
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/dio.html -V wrsw_dio_wb.vhd --cstyle defines --lang vhdl -K ../../sim/dio_timing_regs.vh wrsw_dio.wb
wbgen2 -D wrsw_dio_wb.htm -V wrsw_dio_wb.vhd --cstyle defines --lang vhdl -K ../../sim/dio_timing_regs.vh wrsw_dio.wb
#mkdir -p doc
# wbgen2 -D ./doc/dio.html -V wrsw_dio_wb.vhd --cstyle defines --lang vhdl -p dio_wbgen2_pkg.vhd -H record -K ../../sim/dio_timing_regs.vh wrsw_dio.wb
......@@ -39,6 +39,7 @@ entity wrsw_dio is
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
......
......@@ -531,20 +531,63 @@ peripheral {
-- OUTPUT CONFIGURATION/CONTROL REGISTERS
-----------------------------------------
-- Programmable output or GPIO selection
-- Programmable IO mode selection
reg {
name = "FMC-DIO output configuration register. ";
description = "It allows to choose a programmable output or a standard GPIO output.";
prefix = "out";
name = "FMC-DIO input/output configuration register. ";
description = "It allows to choose the I/0 mode for each channel. \
- [0-1]: The two first bit correspond to which signal its connected: 0 (00) GPIO, 1 (01) DIO core, 2 (10) WRPC core, 3 Undefined\
- [2]: Output Enable Negative (Input enable)\
- [3]: 50 Ohm termination enable";
prefix = "iomode";
field {
name = "channel0";
description = "Channel 0";
prefix = "ch0";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "outmode";
description = "1 for programmable, 0 for GPIO output mode";
prefix = "mode";
name = "channel1";
description = "Channel 1";
prefix = "ch1";
type = SLV;
size = 5;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "channel2";
description = "Channel 2";
prefix = "ch2";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "channel3";
description = "Channel 3";
prefix = "ch3";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "channel4";
description = "Channel 4: Can be used in clock mode";
prefix = "ch4";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
......@@ -770,3 +813,4 @@ peripheral {
};
};
......@@ -29,7 +29,7 @@
<BODY>
<h1 class="heading">wrsw_dio_wb</h1>
<h3>FMC-DIO-5chttla</h3>
<p></p>
<p>This core for adding timing information to a standard GPIO based on WR-CORE information. <br> <br> Operation <br> ~~~~~~~~~~ <br> The registers used on this module allows to time-stamping input values, generate and immediate output or programmed output at a given time. <br><br> * Programmable output: Use seconds and cycles registers for specify trigger time for each channel. Strobe signal is mandatory to latch these values otherwise no output will be generated. <br> * Immediate output could be generate by making active the corresponding bits of the 'Pulse generate immediately' register. <br> * Pulse length can be adjusted by writing a integer value at corresponding registers. The duration will be its value x 8 ns. <br> * There are some few clock cycles that the system is not ready to latch new time information to triggers. This could be checked by checking dio trigger signals. In addition to pooling, interrupts are generated. Note that because is no ready time is about 200 ns, it would almost always available for the PC. <br> * To activate programmable or immediate output generation, please remember to set corresponding bits of the output configuration registers. Otherwise this system behaves as normal GPIO without additional timing features. <br> * FIFOs store seconds and cycles values of time-stamped events. Note that the FIFO depth is 256 and that output generated signals will be also stored in the FIFOs in the same why that external input do. <br> * Interrupts are handle based on EIC registers. FIFOs not empty as well as ready signals of each GPIO are the interrupt sources. <br><br> Todo <br> ~~~~ <br> * Improve documentation. <br><br> Known issues <br> ~~~~~~~~~~~ <br> * None</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
......@@ -49,7 +49,7 @@
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">fmc-dio 4 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">fmc-dio 4 seconds-based trigger for pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">fmc-dio 4 cycles to trigger a pulse generation</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">FMC-DIO output configuration register. </a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">FMC-DIO input/output configuration register. </a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Time-programmable output strobe signal</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">FMC-DIO time trigger is ready to accept a new trigger generation request</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">fmc-dio channel 0 Programmable/immediate output pulse length</a></span><br/>
......@@ -375,13 +375,13 @@ CYC4
REG
</td>
<td >
<A href="#OUT">FMC-DIO output configuration register. </a>
<A href="#IOMODE">FMC-DIO input/output configuration register. </a>
</td>
<td class="td_code">
dio_out
dio_iomode
</td>
<td class="td_code">
OUT
IOMODE
</td>
</tr>
<tr class="tr_odd">
......@@ -2643,7 +2643,7 @@ dio_cyc4_cyc_o[27:0]
</td>
<td class="td_pblock_right">
<b>FMC-DIO output configuration register. :</b>
<b>FMC-DIO input/output configuration register. :</b>
</td>
<td class="td_arrow_right">
......@@ -2660,7 +2660,7 @@ dio_cyc4_cyc_o[27:0]
</td>
<td class="td_pblock_right">
dio_out_mode_o[4:0]
dio_iomode_ch0_o[3:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2672,6 +2672,244 @@ dio_out_mode_o[4:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch0_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch0_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch1_o[3:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch1_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch1_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch2_o[3:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch2_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch2_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch3_o[3:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch3_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch3_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch4_o[3:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch4_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dio_iomode_ch4_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -7893,15 +8131,15 @@ CYC
</b>[<i>read/write</i>]: cycles field
<br>Number of cycles in one second (depends on current clock frequency)
</ul>
<a name="OUT"></a>
<h3><a name="sect_3_16">3.16. FMC-DIO output configuration register. </a></h3>
<a name="IOMODE"></a>
<h3><a name="sect_3_16">3.16. FMC-DIO input/output configuration register. </a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dio_out
dio_iomode
</td>
</tr>
<tr>
......@@ -7917,7 +8155,7 @@ dio_out
<b>C prefix: </b>
</td>
<td class="td_code">
OUT
IOMODE
</td>
</tr>
<tr>
......@@ -7930,7 +8168,7 @@ OUT
</tr>
</table>
<p>
It allows to choose a programmable output or a standard GPIO output.
It allows to choose the I/0 mode for each channel. <br> - [0-1]: The two first bit correspond to which signal its connected: 0 (00) GPIO, 1 (01) DIO core, 2 (10) WRPC core, 3 Undefined<br> - [2]: Output Enable Negative (Input enable)<br> - [3]: 50 Ohm termination enable
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -8026,17 +8264,17 @@ It allows to choose a programmable output or a standard GPIO output.
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=4 class="td_field">
CH4[3:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -8068,29 +8306,29 @@ It allows to choose a programmable output or a standard GPIO output.
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=4 class="td_field">
CH3[3:0]
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=4 class="td_field">
CH2[3:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -8122,17 +8360,17 @@ It allows to choose a programmable output or a standard GPIO output.
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=4 class="td_field">
CH1[3:0]
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=4 class="td_field">
CH0[3:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
MODE[4:0]
<td >
</td>
<td >
......@@ -8150,9 +8388,25 @@ MODE[4:0]
</table>
<ul>
<li><b>
MODE
</b>[<i>read/write</i>]: outmode
<br>1 for programmable, 0 for GPIO output mode
CH0
</b>[<i>read/write</i>]: channel0
<br>Channel 0
<li><b>
CH1
</b>[<i>read/write</i>]: channel1
<br>Channel 1
<li><b>
CH2
</b>[<i>read/write</i>]: channel2
<br>Channel 2
<li><b>
CH3
</b>[<i>read/write</i>]: channel3
<br>Channel 3
<li><b>
CH4
</b>[<i>read/write</i>]: channel4
<br>Channel 4: Can be used in clock mode
</ul>
<a name="LATCH"></a>
<h3><a name="sect_3_17">3.17. Time-programmable output strobe signal</a></h3>
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wrsw_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wrsw_dio.wb
-- Created : Fri Jul 27 17:57:07 2012
-- Created : Wed May 8 14:07:08 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
......@@ -110,8 +110,26 @@ entity wrsw_dio_wb is
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'channel0' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch0_o : out std_logic_vector(3 downto 0);
dio_iomode_ch0_i : in std_logic_vector(3 downto 0);
dio_iomode_ch0_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel1' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch1_o : out std_logic_vector(3 downto 0);
dio_iomode_ch1_i : in std_logic_vector(3 downto 0);
dio_iomode_ch1_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel2' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch2_o : out std_logic_vector(3 downto 0);
dio_iomode_ch2_i : in std_logic_vector(3 downto 0);
dio_iomode_ch2_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel3' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch3_o : out std_logic_vector(3 downto 0);
dio_iomode_ch3_i : in std_logic_vector(3 downto 0);
dio_iomode_ch3_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel4' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch4_o : out std_logic_vector(3 downto 0);
dio_iomode_ch4_i : in std_logic_vector(3 downto 0);
dio_iomode_ch4_load_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
......@@ -194,7 +212,6 @@ signal dio_cyc3_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig4_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh4_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0);
signal dio_out_mode_int : std_logic_vector(4 downto 0);
signal dio_latch_time_ch0_dly0 : std_logic ;
signal dio_latch_time_ch0_int : std_logic ;
signal dio_latch_time_ch1_dly0 : std_logic ;
......@@ -302,7 +319,11 @@ begin
dio_trig4_seconds_int <= "00000000000000000000000000000000";
dio_trigh4_seconds_int <= "00000000";
dio_cyc4_cyc_int <= "0000000000000000000000000000";
dio_out_mode_int <= "00000";
dio_iomode_ch0_load_o <= '0';
dio_iomode_ch1_load_o <= '0';
dio_iomode_ch2_load_o <= '0';
dio_iomode_ch3_load_o <= '0';
dio_iomode_ch4_load_o <= '0';
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
......@@ -337,6 +358,11 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dio_iomode_ch0_load_o <= '0';
dio_iomode_ch1_load_o <= '0';
dio_iomode_ch2_load_o <= '0';
dio_iomode_ch3_load_o <= '0';
dio_iomode_ch4_load_o <= '0';
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
......@@ -347,6 +373,11 @@ begin
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
dio_iomode_ch0_load_o <= '0';
dio_iomode_ch1_load_o <= '0';
dio_iomode_ch2_load_o <= '0';
dio_iomode_ch3_load_o <= '0';
dio_iomode_ch4_load_o <= '0';
dio_pulse_imm_0_int <= dio_pulse_imm_0_int_delay;
dio_pulse_imm_0_int_delay <= '0';
dio_pulse_imm_1_int <= dio_pulse_imm_1_int_delay;
......@@ -608,24 +639,17 @@ begin
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
dio_out_mode_int <= wrdata_reg(4 downto 0);
dio_iomode_ch0_load_o <= '1';
dio_iomode_ch1_load_o <= '1';
dio_iomode_ch2_load_o <= '1';
dio_iomode_ch3_load_o <= '1';
dio_iomode_ch4_load_o <= '1';
end if;
rddata_reg(4 downto 0) <= dio_out_mode_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(3 downto 0) <= dio_iomode_ch0_i;
rddata_reg(7 downto 4) <= dio_iomode_ch1_i;
rddata_reg(11 downto 8) <= dio_iomode_ch2_i;
rddata_reg(15 downto 12) <= dio_iomode_ch3_i;
rddata_reg(19 downto 16) <= dio_iomode_ch4_i;
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
......@@ -648,11 +672,11 @@ begin
dio_latch_time_ch3_int <= wrdata_reg(3);
dio_latch_time_ch4_int <= wrdata_reg(4);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -788,11 +812,11 @@ begin
dio_pulse_imm_4_int <= wrdata_reg(4);
dio_pulse_imm_4_int_delay <= wrdata_reg(4);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -1528,8 +1552,16 @@ begin
dio_trigh4_seconds_o <= dio_trigh4_seconds_int;
-- cycles field
dio_cyc4_cyc_o <= dio_cyc4_cyc_int;
-- outmode
dio_out_mode_o <= dio_out_mode_int;
-- channel0
dio_iomode_ch0_o <= wrdata_reg(3 downto 0);
-- channel1
dio_iomode_ch1_o <= wrdata_reg(7 downto 4);
-- channel2
dio_iomode_ch2_o <= wrdata_reg(11 downto 8);
-- channel3
dio_iomode_ch3_o <= wrdata_reg(15 downto 12);
-- channel4
dio_iomode_ch4_o <= wrdata_reg(19 downto 16);
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
......
......@@ -52,6 +52,7 @@ entity xwrsw_dio is
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
......@@ -283,8 +284,26 @@ architecture rtl of xwrsw_dio is
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
dio_out_mode_o : out std_logic_vector(4 downto 0);
-- Port for unsigned field: 'channel' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch0_o : out std_logic_vector(3 downto 0);
dio_iomode_ch0_i : in std_logic_vector(3 downto 0);
dio_iomode_ch0_load_o : out std_logic;
-- Port for unsigned field: 'channel1' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch1_o : out std_logic_vector(3 downto 0);
dio_iomode_ch1_i : in std_logic_vector(3 downto 0);
dio_iomode_ch1_load_o : out std_logic;
-- Port for unsigned field: 'channel2' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch2_o : out std_logic_vector(3 downto 0);
dio_iomode_ch2_i : in std_logic_vector(3 downto 0);
dio_iomode_ch2_load_o : out std_logic;
-- Port for unsigned field: 'channel3' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch3_o : out std_logic_vector(3 downto 0);
dio_iomode_ch3_i : in std_logic_vector(3 downto 0);
dio_iomode_ch3_load_o : out std_logic;
-- Port for unsigned field: 'channel4' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch4_o : out std_logic_vector(3 downto 0);
dio_iomode_ch4_i : in std_logic_vector(3 downto 0);
dio_iomode_ch4_load_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
......@@ -330,7 +349,8 @@ architecture rtl of xwrsw_dio is
-- Constants declaration
------------------------------------------------------------------------------
constant c_WB_SLAVES_DIO : integer := 4;
constant c_WB_SLAVES_DIO : integer := 4; -- Number of WB slaves in DIO
constant c_IOMODE_NB : integer := 4; -- Number of bit per channel for iomode reg
------------------------------------------------------------------------------
-- Signals declaration
......@@ -370,7 +390,6 @@ architecture rtl of xwrsw_dio is
-- Fifos no-empty interrupts
signal irq_nempty : std_logic_vector (4 downto 0);
-- DEBUG SIGNALS FOR USING seconds time values from dummy_time instead WRPC
signal tm_seconds : std_logic_vector (39 downto 0);
signal tm_cycles : std_logic_vector (27 downto 0);
......@@ -398,7 +417,9 @@ architecture rtl of xwrsw_dio is
signal dio_pulse_prog : std_logic_vector(4 downto 0);
signal dio_pulse_immed : std_logic_vector(4 downto 0);
signal dio_pulse_immed_stb : std_logic_vector(4 downto 0);
signal dio_out_mode : std_logic_vector(4 downto 0);
signal dio_iomode_reg : std_logic_vector(19 downto 0);
signal dio_iomode_o : std_logic_vector(19 downto 0);
signal dio_iomode_load_o : std_logic_vector(4 downto 0);
signal wb_dio_irq : std_logic;
-------------------------------------------------------------------------------
......@@ -592,17 +613,19 @@ begin
end generate immediate_output_with_pulse_length;
gen_pio_assignment: for i in 0 to 4 generate
gpio_in(4*i) <= dio_in_i(i);
gpio_in(c_IOMODE_NB*i) <= dio_in_i(i);
dio_pulse(i) <= '1' when dio_pulse_immed(i) = '1' else dio_pulse_prog(i);
dio_out_o(i) <= dio_pulse(i) when dio_out_mode(i) ='1' else gpio_out(4*i);
dio_oe_n_o(i) <= gpio_out(4*i+1);
dio_term_en_o(i) <= gpio_out(4*i+2);
dio_out_o(i) <= dio_pps_i when (dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i) = "10")
else dio_pulse(i) when (dio_iomode_reg(c_IOMODE_NB*i+1 downto c_IOMODE_NB*i) = "01")
else gpio_out(c_IOMODE_NB*i);
dio_oe_n_o(i) <= dio_iomode_reg(c_IOMODE_NB*i+2);
dio_term_en_o(i) <= dio_iomode_reg(c_IOMODE_NB*i+3);
end generate gen_pio_assignment;
dio_led_bot_o <= gpio_out(28);
dio_led_top_o <= gpio_out(27);
gpio_in(29) <= dio_clk_i;
--gpio_in(29) <= dio_clk_i;
dio_sdn_ck_n_o <= gpio_out(30);
dio_sdn_n_o <= gpio_out(31);
......@@ -708,7 +731,23 @@ begin
dio_trigh4_seconds_o => trig_seconds(4)(39 downto 32),
dio_cyc4_cyc_o => trig_cycles(4),
dio_out_mode_o => dio_out_mode,
dio_iomode_ch0_i => dio_iomode_reg(3 downto 0),
dio_iomode_ch1_i => dio_iomode_reg(7 downto 4),
dio_iomode_ch2_i => dio_iomode_reg(11 downto 8),
dio_iomode_ch3_i => dio_iomode_reg(15 downto 12),
dio_iomode_ch4_i => dio_iomode_reg(19 downto 16),
dio_iomode_ch0_o => dio_iomode_o(3 downto 0),
dio_iomode_ch1_o => dio_iomode_o(7 downto 4),
dio_iomode_ch2_o => dio_iomode_o(11 downto 8),
dio_iomode_ch3_o => dio_iomode_o(15 downto 12),
dio_iomode_ch4_o => dio_iomode_o(19 downto 16),
dio_iomode_ch0_load_o => dio_iomode_load_o(0),
dio_iomode_ch1_load_o => dio_iomode_load_o(1),
dio_iomode_ch2_load_o => dio_iomode_load_o(2),
dio_iomode_ch3_load_o => dio_iomode_load_o(3),
dio_iomode_ch4_load_o => dio_iomode_load_o(4),
dio_latch_time_ch0_o => trig_valid_p1(0),
dio_latch_time_ch1_o => trig_valid_p1(1),
......@@ -717,50 +756,75 @@ begin
dio_latch_time_ch4_o => trig_valid_p1(4),
dio_trig_rdy_i => trig_ready,
irq_trigger_ready_0_i => trig_ready(0),
irq_trigger_ready_0_i => trig_ready(0),
irq_trigger_ready_1_i => trig_ready(1),
irq_trigger_ready_2_i => trig_ready(2),
irq_trigger_ready_3_i => trig_ready(3),
irq_trigger_ready_4_i => trig_ready(4),
dio_prog0_pulse_length_o=> pulse_length(0),
dio_prog0_pulse_length_o=> pulse_length(0),
dio_prog1_pulse_length_o=> pulse_length(1),
dio_prog2_pulse_length_o=> pulse_length(2),
dio_prog3_pulse_length_o=> pulse_length(3),
dio_prog4_pulse_length_o=> pulse_length(4),
dio_pulse_imm_0_o => dio_pulse_immed_stb(0),
dio_pulse_imm_1_o => dio_pulse_immed_stb(1),
dio_pulse_imm_2_o => dio_pulse_immed_stb(2),
dio_pulse_imm_3_o => dio_pulse_immed_stb(3),
dio_pulse_imm_0_o => dio_pulse_immed_stb(0),
dio_pulse_imm_1_o => dio_pulse_immed_stb(1),
dio_pulse_imm_2_o => dio_pulse_immed_stb(2),
dio_pulse_imm_3_o => dio_pulse_immed_stb(3),
dio_pulse_imm_4_o => dio_pulse_immed_stb(4)
);
-- seconds timestamped FIFO-no-empty interrupts
irq_fifos : for i in 0 to 4 generate
irq_nempty(i) <= not dio_tsf_wr_empty(i);
irq_nempty(0) <= not dio_tsf_wr_empty(0);
irq_nempty(1) <= not dio_tsf_wr_empty(1);
irq_nempty(2) <= not dio_tsf_wr_empty(2);
irq_nempty(3) <= not dio_tsf_wr_empty(3);
--disable interrupts when setup in clock mode.
irq_nempty(4) <= not dio_tsf_wr_empty(4) when (dio_iomode_reg(18 downto 16) /= "110");
process(clk_sys_i, rst_n_i)
irq_fifos : for i in 0 to 4 generate
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dio_tsf_wr_req(i) <= '0';
dio_tsf_tag_seconds(i) <= (others => '0');
dio_tsf_tag_cycles(i) <= (others => '0');
dio_tsf_tag_cycles(i) <= (others => '0');
else
if ((tag_valid_p1(i) = '1') AND (dio_tsf_wr_full(i)='0')) then
dio_tsf_wr_req(i) <='1';
dio_tsf_tag_seconds(i) <=tag_seconds(i);
dio_tsf_tag_cycles(i) <=tag_cycles(i);
else
dio_tsf_wr_req(i) <='0';
dio_tsf_wr_req(i) <='0';
end if;
end if;
end if;
end process;
end generate irq_fifos;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
-- Set default configuration for each channel at reset
if rst_n_i = '0' then
dio_iomode_reg(2*c_IOMODE_NB+3 downto 2*c_IOMODE_NB) <= "0010"; -- mode 2 p
dio_iomode_reg(3*c_IOMODE_NB+3 downto 3*c_IOMODE_NB) <= "1100"; -- mode 3 I
dio_iomode_reg(4*c_IOMODE_NB+3 downto 4*c_IOMODE_NB) <= "1110"; -- mode 4 C
else
-- Set up register iomode for each channel
for i in 0 to 4 loop
if (dio_iomode_load_o(i) = '1') then
dio_iomode_reg(c_IOMODE_NB*i+3 downto c_IOMODE_NB*i) <= dio_iomode_o(c_IOMODE_NB*i+3 downto c_IOMODE_NB*i);
end if;
end loop;
end if;
end if;
end process;
-----------------------------------------------------------------------------------
------ signals for debugging
-----------------------------------------------------------------------------------
......
......@@ -368,6 +368,7 @@ architecture rtl of wr_nic_sdb_top is
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
......@@ -1084,6 +1085,7 @@ begin
rst_n_i => local_reset_n,
dio_clk_i => dio_clk,
dio_pps_i => pps,
dio_in_i => dio_in,
dio_out_o => dio_out,
dio_oe_n_o => dio_oe_n_o,
......
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