# wrsw_dio_wb

### FMC-DIO-5chttla

This core for adding timing information to a standard GPIO based on WR-CORE information.
Operation
~~~~~~~~~~
The registers used on this module allows to time-stamping input values, generate and immediate output or programmed output at a given time.
* Programmable output: Use seconds and cycles registers for specify trigger time for each channel. Strobe signal is mandatory to latch these values otherwise no output will be generated.
* Immediate output could be generate by making active the corresponding bits of the 'Pulse generate immediately' register.
* Pulse length can be adjusted by writing a integer value at corresponding registers. The duration will be its value x 8 ns.
* There are some few clock cycles that the system is not ready to latch new time information to triggers. This could be checked by checking dio trigger signals. In addition to pooling, interrupts are generated. Note that because is no ready time is about 200 ns, it would almost always available for the PC.
* To activate programmable or immediate output generation, please remember to set corresponding bits of the output configuration registers. Otherwise this system behaves as normal GPIO without additional timing features.
* FIFOs store seconds and cycles values of time-stamped events. Note that the FIFO depth is 256 and that output generated signals will be also stored in the FIFOs in the same why that external input do.
* Interrupts are handle based on EIC registers. FIFOs not empty as well as ready signals of each GPIO are the interrupt sources.
Todo
~~~~
* Improve documentation.
Known issues
~~~~~~~~~~~
* None

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. fmc-dio 0 seconds-based trigger for pulse generation
3.2. fmc-dio 0 seconds-based trigger for pulse generation
3.3. fmc-dio 0 cycles to trigger a pulse generation
3.4. fmc-dio 1 seconds-based trigger for pulse generation
3.5. fmc-dio 1 seconds-based trigger for pulse generation
3.6. fmc-dio 1 cycles to trigger a pulse generation
3.7. fmc-dio 2 seconds-based trigger for pulse generation
3.8. fmc-dio 2 seconds-based trigger for pulse generation
3.9. fmc-dio 2 cycles to trigger a pulse generation
3.10. fmc-dio 3 seconds-based trigger for pulse generation
3.11. fmc-dio 3 seconds-based trigger for pulse generation
3.12. fmc-dio 3 cycles to trigger a pulse generation
3.13. fmc-dio 4 seconds-based trigger for pulse generation
3.14. fmc-dio 4 seconds-based trigger for pulse generation
3.15. fmc-dio 4 cycles to trigger a pulse generation
3.16. FMC-DIO input/output configuration register.
3.17. Time-programmable output strobe signal
3.18. FMC-DIO time trigger is ready to accept a new trigger generation request
3.19. fmc-dio channel 0 Programmable/immediate output pulse length
3.20. fmc-dio channel 1 Programmable/immediate output pulse length
3.21. fmc-dio channel 2 Programmable/immediate output pulse length
3.22. fmc-dio channel 3 Programmable/immediate output pulse length
3.23. fmc-dio channel 4 Programmable/immediate output pulse length
3.24. Pulse generate immediately
3.25. Interrupt disable register
3.26. Interrupt enable register
3.27. Interrupt mask register
3.28. Interrupt status register
3.29. FIFO 'Timestamp FIFO 0' data output register 0
3.30. FIFO 'Timestamp FIFO 0' data output register 1
3.31. FIFO 'Timestamp FIFO 0' data output register 2
3.32. FIFO 'Timestamp FIFO 0' control/status register
3.33. FIFO 'Timestamp FIFO 1' data output register 0
3.34. FIFO 'Timestamp FIFO 1' data output register 1
3.35. FIFO 'Timestamp FIFO 1' data output register 2
3.36. FIFO 'Timestamp FIFO 1' control/status register
3.37. FIFO 'Timestamp FIFO 2' data output register 0
3.38. FIFO 'Timestamp FIFO 2' data output register 1
3.39. FIFO 'Timestamp FIFO 2' data output register 2
3.40. FIFO 'Timestamp FIFO 2' control/status register
3.41. FIFO 'Timestamp FIFO 3' data output register 0
3.42. FIFO 'Timestamp FIFO 3' data output register 1
3.43. FIFO 'Timestamp FIFO 3' data output register 2
3.44. FIFO 'Timestamp FIFO 3' control/status register
3.45. FIFO 'Timestamp FIFO 4' data output register 0
3.46. FIFO 'Timestamp FIFO 4' data output register 1
3.47. FIFO 'Timestamp FIFO 4' data output register 2
3.48. FIFO 'Timestamp FIFO 4' control/status register
5. Interrupts
5.1. dio fifo not-empty 0
5.2. dio fifo not-empty 1
5.3. dio fifo not-empty 2
5.4. dio fifo not-empty 3
5.5. dio fifo not-empty 4
5.6. Channel 0 trigger ready interrupt
5.7. Channel 1 trigger ready interrupt
5.8. Channel 2 trigger ready interrupt
5.9. Channel 3 trigger ready interrupt
5.10. Channel 4 trigger ready interrupt

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | fmc-dio 0 seconds-based trigger for pulse generation | dio_trig0 | TRIG0
0x1 | REG | fmc-dio 0 seconds-based trigger for pulse generation | dio_trigh0 | TRIGH0
0x2 | REG | fmc-dio 0 cycles to trigger a pulse generation | dio_cyc0 | CYC0
0x3 | REG | fmc-dio 1 seconds-based trigger for pulse generation | dio_trig1 | TRIG1
0x4 | REG | fmc-dio 1 seconds-based trigger for pulse generation | dio_trigh1 | TRIGH1
0x5 | REG | fmc-dio 1 cycles to trigger a pulse generation | dio_cyc1 | CYC1
0x6 | REG | fmc-dio 2 seconds-based trigger for pulse generation | dio_trig2 | TRIG2
0x7 | REG | fmc-dio 2 seconds-based trigger for pulse generation | dio_trigh2 | TRIGH2
0x8 | REG | fmc-dio 2 cycles to trigger a pulse generation | dio_cyc2 | CYC2
0x9 | REG | fmc-dio 3 seconds-based trigger for pulse generation | dio_trig3 | TRIG3
0xa | REG | fmc-dio 3 seconds-based trigger for pulse generation | dio_trigh3 | TRIGH3
0xb | REG | fmc-dio 3 cycles to trigger a pulse generation | dio_cyc3 | CYC3
0xc | REG | fmc-dio 4 seconds-based trigger for pulse generation | dio_trig4 | TRIG4
0xd | REG | fmc-dio 4 seconds-based trigger for pulse generation | dio_trigh4 | TRIGH4
0xe | REG | fmc-dio 4 cycles to trigger a pulse generation | dio_cyc4 | CYC4
0xf | REG | FMC-DIO input/output configuration register. | dio_iomode | IOMODE
0x10 | REG | Time-programmable output strobe signal | dio_latch | LATCH
0x11 | REG | FMC-DIO time trigger is ready to accept a new trigger generation request | dio_trig | TRIG
0x12 | REG | fmc-dio channel 0 Programmable/immediate output pulse length | dio_prog0_pulse | PROG0_PULSE
0x13 | REG | fmc-dio channel 1 Programmable/immediate output pulse length | dio_prog1_pulse | PROG1_PULSE
0x14 | REG | fmc-dio channel 2 Programmable/immediate output pulse length | dio_prog2_pulse | PROG2_PULSE
0x15 | REG | fmc-dio channel 3 Programmable/immediate output pulse length | dio_prog3_pulse | PROG3_PULSE
0x16 | REG | fmc-dio channel 4 Programmable/immediate output pulse length | dio_prog4_pulse | PROG4_PULSE
0x17 | REG | Pulse generate immediately | dio_pulse | PULSE
0x18 | REG | Interrupt disable register | dio_eic_idr | EIC_IDR
0x19 | REG | Interrupt enable register | dio_eic_ier | EIC_IER
0x1a | REG | Interrupt mask register | dio_eic_imr | EIC_IMR
0x1b | REG | Interrupt status register | dio_eic_isr | EIC_ISR
0x1c | FIFOREG | FIFO 'Timestamp FIFO 0' data output register 0 | dio_tsf0_r0 | TSF0_R0
0x1d | FIFOREG | FIFO 'Timestamp FIFO 0' data output register 1 | dio_tsf0_r1 | TSF0_R1
0x1e | FIFOREG | FIFO 'Timestamp FIFO 0' data output register 2 | dio_tsf0_r2 | TSF0_R2
0x1f | REG | FIFO 'Timestamp FIFO 0' control/status register | dio_tsf0_csr | TSF0_CSR
0x20 | FIFOREG | FIFO 'Timestamp FIFO 1' data output register 0 | dio_tsf1_r0 | TSF1_R0
0x21 | FIFOREG | FIFO 'Timestamp FIFO 1' data output register 1 | dio_tsf1_r1 | TSF1_R1
0x22 | FIFOREG | FIFO 'Timestamp FIFO 1' data output register 2 | dio_tsf1_r2 | TSF1_R2
0x23 | REG | FIFO 'Timestamp FIFO 1' control/status register | dio_tsf1_csr | TSF1_CSR
0x24 | FIFOREG | FIFO 'Timestamp FIFO 2' data output register 0 | dio_tsf2_r0 | TSF2_R0
0x25 | FIFOREG | FIFO 'Timestamp FIFO 2' data output register 1 | dio_tsf2_r1 | TSF2_R1
0x26 | FIFOREG | FIFO 'Timestamp FIFO 2' data output register 2 | dio_tsf2_r2 | TSF2_R2
0x27 | REG | FIFO 'Timestamp FIFO 2' control/status register | dio_tsf2_csr | TSF2_CSR
0x28 | FIFOREG | FIFO 'Timestamp FIFO 3' data output register 0 | dio_tsf3_r0 | TSF3_R0
0x29 | FIFOREG | FIFO 'Timestamp FIFO 3' data output register 1 | dio_tsf3_r1 | TSF3_R1
0x2a | FIFOREG | FIFO 'Timestamp FIFO 3' data output register 2 | dio_tsf3_r2 | TSF3_R2
0x2b | REG | FIFO 'Timestamp FIFO 3' control/status register | dio_tsf3_csr | TSF3_CSR
0x2c | FIFOREG | FIFO 'Timestamp FIFO 4' data output register 0 | dio_tsf4_r0 | TSF4_R0
0x2d | FIFOREG | FIFO 'Timestamp FIFO 4' data output register 1 | dio_tsf4_r1 | TSF4_R1
0x2e | FIFOREG | FIFO 'Timestamp FIFO 4' data output register 2 | dio_tsf4_r2 | TSF4_R2
0x2f | REG | FIFO 'Timestamp FIFO 4' control/status register | dio_tsf4_csr | TSF4_CSR

### 2. HDL symbol

→ | rst_n_i |  | Timestamp FIFO 0: |
→ | clk_sys_i |  | dio_tsf0_wr_req_i | ←
⇒ | wb_adr_i[5:0] |  | dio_tsf0_wr_full_o | →
⇒ | wb_dat_i[31:0] |  | dio_tsf0_wr_empty_o | →
⇐ | wb_dat_o[31:0] |  | dio_tsf0_tag_seconds_i[31:0] | ⇐
→ | wb_cyc_i |  | dio_tsf0_tag_secondsh_i[7:0] | ⇐
⇒ | wb_sel_i[3:0] |  | dio_tsf0_tag_cycles_i[27:0] | ⇐
→ | wb_stb_i |  |  |
→ | wb_we_i |  | dio fifo not-empty 0: |
← | wb_ack_o |  | irq_nempty_0_i | ←
← | wb_stall_o |  |  |
← | wb_int_o |  | Timestamp FIFO 1: |
|  |  | dio_tsf1_wr_req_i | ←
|  |  | dio_tsf1_wr_full_o | →
|  |  | dio_tsf1_wr_empty_o | →
|  |  | dio_tsf1_tag_seconds_i[31:0] | ⇐
|  |  | dio_tsf1_tag_secondsh_i[7:0] | ⇐
|  |  | dio_tsf1_tag_cycles_i[27:0] | ⇐
|  |  | dio fifo not-empty 1: |
|  |  | irq_nempty_1_i | ←
|  |  | Timestamp FIFO 2: |
|  |  | dio_tsf2_wr_req_i | ←
|  |  | dio_tsf2_wr_full_o | →
|  |  | dio_tsf2_wr_empty_o | →
|  |  | dio_tsf2_tag_seconds_i[31:0] | ⇐
|  |  | dio_tsf2_tag_secondsh_i[7:0] | ⇐
|  |  | dio_tsf2_tag_cycles_i[27:0] | ⇐
|  |  | dio fifo not-empty 2: |
|  |  | irq_nempty_2_i | ←
|  |  | Timestamp FIFO 3: |
|  |  | dio_tsf3_wr_req_i | ←
|  |  | dio_tsf3_wr_full_o | →
|  |  | dio_tsf3_wr_empty_o | →
|  |  | dio_tsf3_tag_seconds_i[31:0] | ⇐
|  |  | dio_tsf3_tag_secondsh_i[7:0] | ⇐
|  |  | dio_tsf3_tag_cycles_i[27:0] | ⇐
|  |  | dio fifo not-empty 3: |
|  |  | irq_nempty_3_i | ←
|  |  | Timestamp FIFO 4: |
|  |  | dio_tsf4_wr_req_i | ←
|  |  | dio_tsf4_wr_full_o | →
|  |  | dio_tsf4_wr_empty_o | →
|  |  | dio_tsf4_tag_seconds_i[31:0] | ⇐
|  |  | dio_tsf4_tag_secondsh_i[7:0] | ⇐
|  |  | dio_tsf4_tag_cycles_i[27:0] | ⇐
|  |  | dio fifo not-empty 4: |
|  |  | irq_nempty_4_i | ←
|  |  | fmc-dio 0 seconds-based trigger for pulse generation: |
|  |  | dio_trig0_seconds_o[31:0] | ⇒
|  |  | fmc-dio 0 seconds-based trigger for pulse generation: |
|  |  | dio_trigh0_seconds_o[7:0] | ⇒
|  |  | fmc-dio 0 cycles to trigger a pulse generation: |
|  |  | dio_cyc0_cyc_o[27:0] | ⇒
|  |  | fmc-dio 1 seconds-based trigger for pulse generation: |
|  |  | dio_trig1_seconds_o[31:0] | ⇒
|  |  | fmc-dio 1 seconds-based trigger for pulse generation: |
|  |  | dio_trigh1_seconds_o[7:0] | ⇒
|  |  | fmc-dio 1 cycles to trigger a pulse generation: |
|  |  | dio_cyc1_cyc_o[27:0] | ⇒
|  |  | fmc-dio 2 seconds-based trigger for pulse generation: |
|  |  | dio_trig2_seconds_o[31:0] | ⇒
|  |  | fmc-dio 2 seconds-based trigger for pulse generation: |
|  |  | dio_trigh2_seconds_o[7:0] | ⇒
|  |  | fmc-dio 2 cycles to trigger a pulse generation: |
|  |  | dio_cyc2_cyc_o[27:0] | ⇒
|  |  | fmc-dio 3 seconds-based trigger for pulse generation: |
|  |  | dio_trig3_seconds_o[31:0] | ⇒
|  |  | fmc-dio 3 seconds-based trigger for pulse generation: |
|  |  | dio_trigh3_seconds_o[7:0] | ⇒
|  |  | fmc-dio 3 cycles to trigger a pulse generation: |
|  |  | dio_cyc3_cyc_o[27:0] | ⇒
|  |  | fmc-dio 4 seconds-based trigger for pulse generation: |
|  |  | dio_trig4_seconds_o[31:0] | ⇒
|  |  | fmc-dio 4 seconds-based trigger for pulse generation: |
|  |  | dio_trigh4_seconds_o[7:0] | ⇒
|  |  | fmc-dio 4 cycles to trigger a pulse generation: |
|  |  | dio_cyc4_cyc_o[27:0] | ⇒
|  |  | FMC-DIO input/output configuration register. : |
|  |  | dio_iomode_ch0_o[3:0] | ⇒
|  |  | dio_iomode_ch0_i[3:0] | ⇐
|  |  | dio_iomode_ch0_load_o | →
|  |  | dio_iomode_ch1_o[3:0] | ⇒
|  |  | dio_iomode_ch1_i[3:0] | ⇐
|  |  | dio_iomode_ch1_load_o | →
|  |  | dio_iomode_ch2_o[3:0] | ⇒
|  |  | dio_iomode_ch2_i[3:0] | ⇐
|  |  | dio_iomode_ch2_load_o | →
|  |  | dio_iomode_ch3_o[3:0] | ⇒
|  |  | dio_iomode_ch3_i[3:0] | ⇐
|  |  | dio_iomode_ch3_load_o | →
|  |  | dio_iomode_ch4_o[3:0] | ⇒
|  |  | dio_iomode_ch4_i[3:0] | ⇐
|  |  | dio_iomode_ch4_load_o | →
|  |  | Time-programmable output strobe signal: |
|  |  | dio_latch_time_ch0_o | →
|  |  | dio_latch_time_ch1_o | →
|  |  | dio_latch_time_ch2_o | →
|  |  | dio_latch_time_ch3_o | →
|  |  | dio_latch_time_ch4_o | →
|  |  | FMC-DIO time trigger is ready to accept a new trigger generation request: |
|  |  | dio_trig_rdy_i[4:0] | ⇐
|  |  | Channel 0 trigger ready interrupt: |
|  |  | irq_trigger_ready_0_i | ←
|  |  | Channel 1 trigger ready interrupt: |
|  |  | irq_trigger_ready_1_i | ←
|  |  | Channel 2 trigger ready interrupt: |
|  |  | irq_trigger_ready_2_i | ←
|  |  | Channel 3 trigger ready interrupt: |
|  |  | irq_trigger_ready_3_i | ←
|  |  | Channel 4 trigger ready interrupt: |
|  |  | irq_trigger_ready_4_i | ←
|  |  | fmc-dio channel 0 Programmable/immediate output pulse length: |
|  |  | dio_prog0_pulse_length_o[27:0] | ⇒
|  |  | fmc-dio channel 1 Programmable/immediate output pulse length: |
|  |  | dio_prog1_pulse_length_o[27:0] | ⇒
|  |  | fmc-dio channel 2 Programmable/immediate output pulse length: |
|  |  | dio_prog2_pulse_length_o[27:0] | ⇒
|  |  | fmc-dio channel 3 Programmable/immediate output pulse length: |
|  |  | dio_prog3_pulse_length_o[27:0] | ⇒
|  |  | fmc-dio channel 4 Programmable/immediate output pulse length: |
|  |  | dio_prog4_pulse_length_o[27:0] | ⇒
|  |  | Pulse generate immediately: |
|  |  | dio_pulse_imm_0_o | →
|  |  | dio_pulse_imm_1_o | →
|  |  | dio_pulse_imm_2_o | →
|  |  | dio_pulse_imm_3_o | →
|  |  | dio_pulse_imm_4_o | →
|  |  | FIFO 'Timestamp FIFO 0' data output register 0: |
|  |  | FIFO 'Timestamp FIFO 0' data output register 1: |
|  |  | FIFO 'Timestamp FIFO 0' data output register 2: |
|  |  | FIFO 'Timestamp FIFO 1' data output register 0: |
|  |  | FIFO 'Timestamp FIFO 1' data output register 1: |
|  |  | FIFO 'Timestamp FIFO 1' data output register 2: |
|  |  | FIFO 'Timestamp FIFO 2' data output register 0: |
|  |  | FIFO 'Timestamp FIFO 2' data output register 1: |
|  |  | FIFO 'Timestamp FIFO 2' data output register 2: |
|  |  | FIFO 'Timestamp FIFO 3' data output register 0: |
|  |  | FIFO 'Timestamp FIFO 3' data output register 1: |
|  |  | FIFO 'Timestamp FIFO 3' data output register 2: |
|  |  | FIFO 'Timestamp FIFO 4' data output register 0: |
|  |  | FIFO 'Timestamp FIFO 4' data output register 1: |
|  |  | FIFO 'Timestamp FIFO 4' data output register 2: |

### 3. Register description

### 3.1. fmc-dio 0 seconds-based trigger for pulse generation

HW prefix: | dio_trig0
HW address: | 0x0
C prefix: | TRIG0
C offset: | 0x0

trigger seconds value for dio output (LSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  TBD

### 3.2. fmc-dio 0 seconds-based trigger for pulse generation

HW prefix: | dio_trigh0
HW address: | 0x1
C prefix: | TRIGH0
C offset: | 0x4

trigger seconds value for dio output (MSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  Number of seconds

### 3.3. fmc-dio 0 cycles to trigger a pulse generation

HW prefix: | dio_cyc0
HW address: | 0x2
C prefix: | CYC0
C offset: | 0x8

sub-second accuracy values (clock cycles) to trigger dio output channels.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CYC[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CYC[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CYC[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CYC[7:0] |  |  |  |  |  |  |

- CYC [read/write]: cycles field
  Number of cycles in one second (depends on current clock frequency)

### 3.4. fmc-dio 1 seconds-based trigger for pulse generation

HW prefix: | dio_trig1
HW address: | 0x3
C prefix: | TRIG1
C offset: | 0xc

trigger seconds value for dio output (LSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  TBD

### 3.5. fmc-dio 1 seconds-based trigger for pulse generation

HW prefix: | dio_trigh1
HW address: | 0x4
C prefix: | TRIGH1
C offset: | 0x10

trigger seconds value for dio output (MSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  Number of seconds

### 3.6. fmc-dio 1 cycles to trigger a pulse generation

HW prefix: | dio_cyc1
HW address: | 0x5
C prefix: | CYC1
C offset: | 0x14

sub-second accuracy values (clock cycles) to trigger dio output channels.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CYC[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CYC[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CYC[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CYC[7:0] |  |  |  |  |  |  |

- CYC [read/write]: cycles field
  Number of cycles in one second (depends on current clock frequency)

### 3.7. fmc-dio 2 seconds-based trigger for pulse generation

HW prefix: | dio_trig2
HW address: | 0x6
C prefix: | TRIG2
C offset: | 0x18

trigger seconds value for dio output (LSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  TBD

### 3.8. fmc-dio 2 seconds-based trigger for pulse generation

HW prefix: | dio_trigh2
HW address: | 0x7
C prefix: | TRIGH2
C offset: | 0x1c

trigger seconds value for dio output (MSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  Number of seconds

### 3.9. fmc-dio 2 cycles to trigger a pulse generation

HW prefix: | dio_cyc2
HW address: | 0x8
C prefix: | CYC2
C offset: | 0x20

sub-second accuracy values (clock cycles) to trigger dio output channels.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CYC[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CYC[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CYC[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CYC[7:0] |  |  |  |  |  |  |

- CYC [read/write]: cycles field
  Number of cycles in one second (depends on current clock frequency)

### 3.10. fmc-dio 3 seconds-based trigger for pulse generation

HW prefix: | dio_trig3
HW address: | 0x9
C prefix: | TRIG3
C offset: | 0x24

trigger seconds value for dio output (LSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  TBD

### 3.11. fmc-dio 3 seconds-based trigger for pulse generation

HW prefix: | dio_trigh3
HW address: | 0xa
C prefix: | TRIGH3
C offset: | 0x28

trigger seconds value for dio output (MSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  Number of seconds

### 3.12. fmc-dio 3 cycles to trigger a pulse generation

HW prefix: | dio_cyc3
HW address: | 0xb
C prefix: | CYC3
C offset: | 0x2c

sub-second accuracy values (clock cycles) to trigger dio output channels.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CYC[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CYC[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CYC[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CYC[7:0] |  |  |  |  |  |  |

- CYC [read/write]: cycles field
  Number of cycles in one second (depends on current clock frequency)

### 3.13. fmc-dio 4 seconds-based trigger for pulse generation

HW prefix: | dio_trig4
HW address: | 0xc
C prefix: | TRIG4
C offset: | 0x30

trigger seconds value for dio output (LSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  TBD

### 3.14. fmc-dio 4 seconds-based trigger for pulse generation

HW prefix: | dio_trigh4
HW address: | 0xd
C prefix: | TRIGH4
C offset: | 0x34

trigger seconds value for dio output (MSB).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SECONDS[7:0] |  |  |  |  |  |  |

- SECONDS [read/write]: seconds field
  Number of seconds

### 3.15. fmc-dio 4 cycles to trigger a pulse generation

HW prefix: | dio_cyc4
HW address: | 0xe
C prefix: | CYC4
C offset: | 0x38

sub-second accuracy values (clock cycles) to trigger dio output channels.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CYC[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CYC[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CYC[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CYC[7:0] |  |  |  |  |  |  |

- CYC [read/write]: cycles field
  Number of cycles in one second (depends on current clock frequency)

### 3.16. FMC-DIO input/output configuration register.

HW prefix: | dio_iomode
HW address: | 0xf
C prefix: | IOMODE
C offset: | 0x3c

It allows to choose the I/0 mode for each channel.
- [0-1]: The two first bit correspond to which signal its connected: 0 (00) GPIO, 1 (01) DIO core, 2 (10) WRPC core, 3 Undefined
- [2]: Output Enable Negative (Input enable)
- [3]: 50 Ohm termination enable

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | CH4[3:0] |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH3[3:0] | CH2[3:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH1[3:0] | CH0[3:0] |  |  |  |  |  |

- CH0 [read/write]: channel0
  Channel 0
- CH1 [read/write]: channel1
  Channel 1
- CH2 [read/write]: channel2
  Channel 2
- CH3 [read/write]: channel3
  Channel 3
- CH4 [read/write]: channel4
  Channel 4: Can be used in clock mode

### 3.17. Time-programmable output strobe signal

HW prefix: | dio_latch
HW address: | 0x10
C prefix: | LATCH
C offset: | 0x40

It is used to latch second/cycles values generation just 1 clock cycle output

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | TIME_CH4 | TIME_CH3 | TIME_CH2 | TIME_CH1 | TIME_CH0

- TIME_CH0 [write-only]: Sincle-cycle strobe
  It generates a one-clock cycle pulse for programmable time latching
- TIME_CH1 [write-only]: Sincle-cycle strobe
  It generates a one-clock cycle pulse for programmable time latching
- TIME_CH2 [write-only]: Sincle-cycle strobe
  It generates a one-clock cycle pulse for programmable time latching
- TIME_CH3 [write-only]: Sincle-cycle strobe
  It generates a one-clock cycle pulse for programmable time latching
- TIME_CH4 [write-only]: Sincle-cycle strobe
  It generates a one-clock cycle pulse for programmable time latching

### 3.18. FMC-DIO time trigger is ready to accept a new trigger generation request

HW prefix: | dio_trig
HW address: | 0x11
C prefix: | TRIG
C offset: | 0x44

ready state, waiting new trigger commands for dio output.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | RDY[4:0] |  |  |  |

- RDY [read-only]: trig_rdy field
  TBD

### 3.19. fmc-dio channel 0 Programmable/immediate output pulse length

HW prefix: | dio_prog0_pulse
HW address: | 0x12
C prefix: | PROG0_PULSE
C offset: | 0x48

Number of clk_ref clock ticks that output will be active

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | LENGTH[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LENGTH[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LENGTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LENGTH[7:0] |  |  |  |  |  |  |

- LENGTH [read/write]: number of ticks field for channel 0
  ticks number

### 3.20. fmc-dio channel 1 Programmable/immediate output pulse length

HW prefix: | dio_prog1_pulse
HW address: | 0x13
C prefix: | PROG1_PULSE
C offset: | 0x4c

Number of clk_ref clock ticks that output will be active

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | LENGTH[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LENGTH[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LENGTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LENGTH[7:0] |  |  |  |  |  |  |

- LENGTH [read/write]: number of ticks field for channel 1
  ticks number

### 3.21. fmc-dio channel 2 Programmable/immediate output pulse length

HW prefix: | dio_prog2_pulse
HW address: | 0x14
C prefix: | PROG2_PULSE
C offset: | 0x50

Number of clk_ref clock ticks that output will be active

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | LENGTH[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LENGTH[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LENGTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LENGTH[7:0] |  |  |  |  |  |  |

- LENGTH [read/write]: number of ticks field for channel 2
  ticks number

### 3.22. fmc-dio channel 3 Programmable/immediate output pulse length

HW prefix: | dio_prog3_pulse
HW address: | 0x15
C prefix: | PROG3_PULSE
C offset: | 0x54

Number of clk_ref clock ticks that output will be active

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | LENGTH[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LENGTH[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LENGTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LENGTH[7:0] |  |  |  |  |  |  |

- LENGTH [read/write]: number of ticks field for channel 3
  ticks number

### 3.23. fmc-dio channel 4 Programmable/immediate output pulse length

HW prefix: | dio_prog4_pulse
HW address: | 0x16
C prefix: | PROG4_PULSE
C offset: | 0x58

Number of clk_ref clock ticks that output will be active

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | LENGTH[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
LENGTH[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LENGTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LENGTH[7:0] |  |  |  |  |  |  |

- LENGTH [read/write]: number of ticks field for channel 4
  ticks number

### 3.24. Pulse generate immediately

HW prefix: | dio_pulse
HW address: | 0x17
C prefix: | PULSE
C offset: | 0x5c

It is used to generate a pulse immediately

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | IMM_4 | IMM_3 | IMM_2 | IMM_1 | IMM_0

- IMM_0 [write-only]: pulse_gen_now_0
  It generates a pulse
- IMM_1 [write-only]: pulse_gen_now_1
  It generates a pulse
- IMM_2 [write-only]: pulse_gen_now_2
  It generates a pulse
- IMM_3 [write-only]: pulse_gen_now_3
  It generates a pulse
- IMM_4 [write-only]: pulse_gen_now_4
  It generates a pulse

### 3.25. Interrupt disable register

HW prefix: | dio_eic_idr
HW address: | 0x18
C prefix: | EIC_IDR
C offset: | 0x60

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TRIGGER_READY_4 | TRIGGER_READY_3

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIGGER_READY_2 | TRIGGER_READY_1 | TRIGGER_READY_0 | NEMPTY_4 | NEMPTY_3 | NEMPTY_2 | NEMPTY_1 | NEMPTY_0

- NEMPTY_0 [write-only]: dio fifo not-empty 0
  write 1: disable interrupt 'dio fifo not-empty 0'
  write 0: no effect
- NEMPTY_1 [write-only]: dio fifo not-empty 1
  write 1: disable interrupt 'dio fifo not-empty 1'
  write 0: no effect
- NEMPTY_2 [write-only]: dio fifo not-empty 2
  write 1: disable interrupt 'dio fifo not-empty 2'
  write 0: no effect
- NEMPTY_3 [write-only]: dio fifo not-empty 3
  write 1: disable interrupt 'dio fifo not-empty 3'
  write 0: no effect
- NEMPTY_4 [write-only]: dio fifo not-empty 4
  write 1: disable interrupt 'dio fifo not-empty 4'
  write 0: no effect
- TRIGGER_READY_0 [write-only]: Channel 0 trigger ready interrupt
  write 1: disable interrupt 'Channel 0 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_1 [write-only]: Channel 1 trigger ready interrupt
  write 1: disable interrupt 'Channel 1 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_2 [write-only]: Channel 2 trigger ready interrupt
  write 1: disable interrupt 'Channel 2 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_3 [write-only]: Channel 3 trigger ready interrupt
  write 1: disable interrupt 'Channel 3 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_4 [write-only]: Channel 4 trigger ready interrupt
  write 1: disable interrupt 'Channel 4 trigger ready interrupt'
  write 0: no effect

### 3.26. Interrupt enable register

HW prefix: | dio_eic_ier
HW address: | 0x19
C prefix: | EIC_IER
C offset: | 0x64

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TRIGGER_READY_4 | TRIGGER_READY_3

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIGGER_READY_2 | TRIGGER_READY_1 | TRIGGER_READY_0 | NEMPTY_4 | NEMPTY_3 | NEMPTY_2 | NEMPTY_1 | NEMPTY_0

- NEMPTY_0 [write-only]: dio fifo not-empty 0
  write 1: enable interrupt 'dio fifo not-empty 0'
  write 0: no effect
- NEMPTY_1 [write-only]: dio fifo not-empty 1
  write 1: enable interrupt 'dio fifo not-empty 1'
  write 0: no effect
- NEMPTY_2 [write-only]: dio fifo not-empty 2
  write 1: enable interrupt 'dio fifo not-empty 2'
  write 0: no effect
- NEMPTY_3 [write-only]: dio fifo not-empty 3
  write 1: enable interrupt 'dio fifo not-empty 3'
  write 0: no effect
- NEMPTY_4 [write-only]: dio fifo not-empty 4
  write 1: enable interrupt 'dio fifo not-empty 4'
  write 0: no effect
- TRIGGER_READY_0 [write-only]: Channel 0 trigger ready interrupt
  write 1: enable interrupt 'Channel 0 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_1 [write-only]: Channel 1 trigger ready interrupt
  write 1: enable interrupt 'Channel 1 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_2 [write-only]: Channel 2 trigger ready interrupt
  write 1: enable interrupt 'Channel 2 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_3 [write-only]: Channel 3 trigger ready interrupt
  write 1: enable interrupt 'Channel 3 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_4 [write-only]: Channel 4 trigger ready interrupt
  write 1: enable interrupt 'Channel 4 trigger ready interrupt'
  write 0: no effect

### 3.27. Interrupt mask register

HW prefix: | dio_eic_imr
HW address: | 0x1a
C prefix: | EIC_IMR
C offset: | 0x68

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TRIGGER_READY_4 | TRIGGER_READY_3

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIGGER_READY_2 | TRIGGER_READY_1 | TRIGGER_READY_0 | NEMPTY_4 | NEMPTY_3 | NEMPTY_2 | NEMPTY_1 | NEMPTY_0

- NEMPTY_0 [read-only]: dio fifo not-empty 0
  read 1: interrupt 'dio fifo not-empty 0' is enabled
  read 0: interrupt 'dio fifo not-empty 0' is disabled
- NEMPTY_1 [read-only]: dio fifo not-empty 1
  read 1: interrupt 'dio fifo not-empty 1' is enabled
  read 0: interrupt 'dio fifo not-empty 1' is disabled
- NEMPTY_2 [read-only]: dio fifo not-empty 2
  read 1: interrupt 'dio fifo not-empty 2' is enabled
  read 0: interrupt 'dio fifo not-empty 2' is disabled
- NEMPTY_3 [read-only]: dio fifo not-empty 3
  read 1: interrupt 'dio fifo not-empty 3' is enabled
  read 0: interrupt 'dio fifo not-empty 3' is disabled
- NEMPTY_4 [read-only]: dio fifo not-empty 4
  read 1: interrupt 'dio fifo not-empty 4' is enabled
  read 0: interrupt 'dio fifo not-empty 4' is disabled
- TRIGGER_READY_0 [read-only]: Channel 0 trigger ready interrupt
  read 1: interrupt 'Channel 0 trigger ready interrupt' is enabled
  read 0: interrupt 'Channel 0 trigger ready interrupt' is disabled
- TRIGGER_READY_1 [read-only]: Channel 1 trigger ready interrupt
  read 1: interrupt 'Channel 1 trigger ready interrupt' is enabled
  read 0: interrupt 'Channel 1 trigger ready interrupt' is disabled
- TRIGGER_READY_2 [read-only]: Channel 2 trigger ready interrupt
  read 1: interrupt 'Channel 2 trigger ready interrupt' is enabled
  read 0: interrupt 'Channel 2 trigger ready interrupt' is disabled
- TRIGGER_READY_3 [read-only]: Channel 3 trigger ready interrupt
  read 1: interrupt 'Channel 3 trigger ready interrupt' is enabled
  read 0: interrupt 'Channel 3 trigger ready interrupt' is disabled
- TRIGGER_READY_4 [read-only]: Channel 4 trigger ready interrupt
  read 1: interrupt 'Channel 4 trigger ready interrupt' is enabled
  read 0: interrupt 'Channel 4 trigger ready interrupt' is disabled

### 3.28. Interrupt status register

HW prefix: | dio_eic_isr
HW address: | 0x1b
C prefix: | EIC_ISR
C offset: | 0x6c

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | TRIGGER_READY_4 | TRIGGER_READY_3

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIGGER_READY_2 | TRIGGER_READY_1 | TRIGGER_READY_0 | NEMPTY_4 | NEMPTY_3 | NEMPTY_2 | NEMPTY_1 | NEMPTY_0

- NEMPTY_0 [read/write]: dio fifo not-empty 0
  read 1: interrupt 'dio fifo not-empty 0' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'dio fifo not-empty 0'
  write 0: no effect
- NEMPTY_1 [read/write]: dio fifo not-empty 1
  read 1: interrupt 'dio fifo not-empty 1' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'dio fifo not-empty 1'
  write 0: no effect
- NEMPTY_2 [read/write]: dio fifo not-empty 2
  read 1: interrupt 'dio fifo not-empty 2' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'dio fifo not-empty 2'
  write 0: no effect
- NEMPTY_3 [read/write]: dio fifo not-empty 3
  read 1: interrupt 'dio fifo not-empty 3' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'dio fifo not-empty 3'
  write 0: no effect
- NEMPTY_4 [read/write]: dio fifo not-empty 4
  read 1: interrupt 'dio fifo not-empty 4' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'dio fifo not-empty 4'
  write 0: no effect
- TRIGGER_READY_0 [read/write]: Channel 0 trigger ready interrupt
  read 1: interrupt 'Channel 0 trigger ready interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'Channel 0 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_1 [read/write]: Channel 1 trigger ready interrupt
  read 1: interrupt 'Channel 1 trigger ready interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'Channel 1 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_2 [read/write]: Channel 2 trigger ready interrupt
  read 1: interrupt 'Channel 2 trigger ready interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'Channel 2 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_3 [read/write]: Channel 3 trigger ready interrupt
  read 1: interrupt 'Channel 3 trigger ready interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'Channel 3 trigger ready interrupt'
  write 0: no effect
- TRIGGER_READY_4 [read/write]: Channel 4 trigger ready interrupt
  read 1: interrupt 'Channel 4 trigger ready interrupt' is pending
  read 0: interrupt not pending
  write 1: clear interrupt 'Channel 4 trigger ready interrupt'
  write 0: no effect

### 3.29. FIFO 'Timestamp FIFO 0' data output register 0

HW prefix: | dio_tsf0_r0
HW address: | 0x1c
C prefix: | TSF0_R0
C offset: | 0x70

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TAG_SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDS[7:0] |  |  |  |  |  |  |

- TAG_SECONDS [read-only]: seconds time

### 3.30. FIFO 'Timestamp FIFO 0' data output register 1

HW prefix: | dio_tsf0_r1
HW address: | 0x1d
C prefix: | TSF0_R1
C offset: | 0x74

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDSH[7:0] |  |  |  |  |  |  |

- TAG_SECONDSH [read-only]: seconds time H

### 3.31. FIFO 'Timestamp FIFO 0' data output register 2

HW prefix: | dio_tsf0_r2
HW address: | 0x1e
C prefix: | TSF0_R2
C offset: | 0x78

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TAG_CYCLES[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_CYCLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_CYCLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_CYCLES[7:0] |  |  |  |  |  |  |

- TAG_CYCLES [read-only]: Sub-second accuracy

### 3.32. FIFO 'Timestamp FIFO 0' control/status register

HW prefix: | dio_tsf0_csr
HW address: | 0x1f
C prefix: | TSF0_CSR
C offset: | 0x7c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | EMPTY | FULL

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
USEDW[7:0] |  |  |  |  |  |  |

- FULL [read-only]: FIFO full flag
  1: FIFO 'Timestamp FIFO 0' is full
  0: FIFO is not full
- EMPTY [read-only]: FIFO empty flag
  1: FIFO 'Timestamp FIFO 0' is empty
  0: FIFO is not empty
- USEDW [read-only]: FIFO counter
  Number of data records currently being stored in FIFO 'Timestamp FIFO 0'

### 3.33. FIFO 'Timestamp FIFO 1' data output register 0

HW prefix: | dio_tsf1_r0
HW address: | 0x20
C prefix: | TSF1_R0
C offset: | 0x80

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TAG_SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDS[7:0] |  |  |  |  |  |  |

- TAG_SECONDS [read-only]: seconds time

### 3.34. FIFO 'Timestamp FIFO 1' data output register 1

HW prefix: | dio_tsf1_r1
HW address: | 0x21
C prefix: | TSF1_R1
C offset: | 0x84

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDSH[7:0] |  |  |  |  |  |  |

- TAG_SECONDSH [read-only]: seconds time H

### 3.35. FIFO 'Timestamp FIFO 1' data output register 2

HW prefix: | dio_tsf1_r2
HW address: | 0x22
C prefix: | TSF1_R2
C offset: | 0x88

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TAG_CYCLES[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_CYCLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_CYCLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_CYCLES[7:0] |  |  |  |  |  |  |

- TAG_CYCLES [read-only]: Sub-second accuracy

### 3.36. FIFO 'Timestamp FIFO 1' control/status register

HW prefix: | dio_tsf1_csr
HW address: | 0x23
C prefix: | TSF1_CSR
C offset: | 0x8c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | EMPTY | FULL

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
USEDW[7:0] |  |  |  |  |  |  |

- FULL [read-only]: FIFO full flag
  1: FIFO 'Timestamp FIFO 1' is full
  0: FIFO is not full
- EMPTY [read-only]: FIFO empty flag
  1: FIFO 'Timestamp FIFO 1' is empty
  0: FIFO is not empty
- USEDW [read-only]: FIFO counter
  Number of data records currently being stored in FIFO 'Timestamp FIFO 1'

### 3.37. FIFO 'Timestamp FIFO 2' data output register 0

HW prefix: | dio_tsf2_r0
HW address: | 0x24
C prefix: | TSF2_R0
C offset: | 0x90

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TAG_SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDS[7:0] |  |  |  |  |  |  |

- TAG_SECONDS [read-only]: seconds time

### 3.38. FIFO 'Timestamp FIFO 2' data output register 1

HW prefix: | dio_tsf2_r1
HW address: | 0x25
C prefix: | TSF2_R1
C offset: | 0x94

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDSH[7:0] |  |  |  |  |  |  |

- TAG_SECONDSH [read-only]: seconds time H

### 3.39. FIFO 'Timestamp FIFO 2' data output register 2

HW prefix: | dio_tsf2_r2
HW address: | 0x26
C prefix: | TSF2_R2
C offset: | 0x98

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TAG_CYCLES[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_CYCLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_CYCLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_CYCLES[7:0] |  |  |  |  |  |  |

- TAG_CYCLES [read-only]: Sub-second accuracy

### 3.40. FIFO 'Timestamp FIFO 2' control/status register

HW prefix: | dio_tsf2_csr
HW address: | 0x27
C prefix: | TSF2_CSR
C offset: | 0x9c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | EMPTY | FULL

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
USEDW[7:0] |  |  |  |  |  |  |

- FULL [read-only]: FIFO full flag
  1: FIFO 'Timestamp FIFO 2' is full
  0: FIFO is not full
- EMPTY [read-only]: FIFO empty flag
  1: FIFO 'Timestamp FIFO 2' is empty
  0: FIFO is not empty
- USEDW [read-only]: FIFO counter
  Number of data records currently being stored in FIFO 'Timestamp FIFO 2'

### 3.41. FIFO 'Timestamp FIFO 3' data output register 0

HW prefix: | dio_tsf3_r0
HW address: | 0x28
C prefix: | TSF3_R0
C offset: | 0xa0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TAG_SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDS[7:0] |  |  |  |  |  |  |

- TAG_SECONDS [read-only]: seconds time

### 3.42. FIFO 'Timestamp FIFO 3' data output register 1

HW prefix: | dio_tsf3_r1
HW address: | 0x29
C prefix: | TSF3_R1
C offset: | 0xa4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDSH[7:0] |  |  |  |  |  |  |

- TAG_SECONDSH [read-only]: seconds time H

### 3.43. FIFO 'Timestamp FIFO 3' data output register 2

HW prefix: | dio_tsf3_r2
HW address: | 0x2a
C prefix: | TSF3_R2
C offset: | 0xa8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TAG_CYCLES[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_CYCLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_CYCLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_CYCLES[7:0] |  |  |  |  |  |  |

- TAG_CYCLES [read-only]: Sub-second accuracy

### 3.44. FIFO 'Timestamp FIFO 3' control/status register

HW prefix: | dio_tsf3_csr
HW address: | 0x2b
C prefix: | TSF3_CSR
C offset: | 0xac

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | EMPTY | FULL

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
USEDW[7:0] |  |  |  |  |  |  |

- FULL [read-only]: FIFO full flag
  1: FIFO 'Timestamp FIFO 3' is full
  0: FIFO is not full
- EMPTY [read-only]: FIFO empty flag
  1: FIFO 'Timestamp FIFO 3' is empty
  0: FIFO is not empty
- USEDW [read-only]: FIFO counter
  Number of data records currently being stored in FIFO 'Timestamp FIFO 3'

### 3.45. FIFO 'Timestamp FIFO 4' data output register 0

HW prefix: | dio_tsf4_r0
HW address: | 0x2c
C prefix: | TSF4_R0
C offset: | 0xb0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TAG_SECONDS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_SECONDS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_SECONDS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDS[7:0] |  |  |  |  |  |  |

- TAG_SECONDS [read-only]: seconds time

### 3.46. FIFO 'Timestamp FIFO 4' data output register 1

HW prefix: | dio_tsf4_r1
HW address: | 0x2d
C prefix: | TSF4_R1
C offset: | 0xb4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_SECONDSH[7:0] |  |  |  |  |  |  |

- TAG_SECONDSH [read-only]: seconds time H

### 3.47. FIFO 'Timestamp FIFO 4' data output register 2

HW prefix: | dio_tsf4_r2
HW address: | 0x2e
C prefix: | TSF4_R2
C offset: | 0xb8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TAG_CYCLES[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TAG_CYCLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TAG_CYCLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAG_CYCLES[7:0] |  |  |  |  |  |  |

- TAG_CYCLES [read-only]: Sub-second accuracy

### 3.48. FIFO 'Timestamp FIFO 4' control/status register

HW prefix: | dio_tsf4_csr
HW address: | 0x2f
C prefix: | TSF4_CSR
C offset: | 0xbc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | EMPTY | FULL

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
USEDW[7:0] |  |  |  |  |  |  |

- FULL [read-only]: FIFO full flag
  1: FIFO 'Timestamp FIFO 4' is full
  0: FIFO is not full
- EMPTY [read-only]: FIFO empty flag
  1: FIFO 'Timestamp FIFO 4' is empty
  0: FIFO is not empty
- USEDW [read-only]: FIFO counter
  Number of data records currently being stored in FIFO 'Timestamp FIFO 4'

### 5. Interrupts

### 5.1. dio fifo not-empty 0

HW prefix: | dio_nempty_0
C prefix: | NEMPTY_0
Trigger: | high level

Interrupt active when dio input FIFO contains any timestamps.

### 5.2. dio fifo not-empty 1

HW prefix: | dio_nempty_1
C prefix: | NEMPTY_1
Trigger: | high level

Interrupt active when dio input FIFO contains any timestamps.

### 5.3. dio fifo not-empty 2

HW prefix: | dio_nempty_2
C prefix: | NEMPTY_2
Trigger: | high level

Interrupt active when dio input FIFO contains any timestamps.

### 5.4. dio fifo not-empty 3

HW prefix: | dio_nempty_3
C prefix: | NEMPTY_3
Trigger: | high level

Interrupt active when dio input FIFO contains any timestamps.

### 5.5. dio fifo not-empty 4

HW prefix: | dio_nempty_4
C prefix: | NEMPTY_4
Trigger: | high level

Interrupt active when dio input FIFO contains any timestamps.

### 5.6. Channel 0 trigger ready interrupt

HW prefix: | dio_trigger_ready_0
C prefix: | TRIGGER_READY_0
Trigger: | high level

Interrupt active when time-programmable output channels accept new time trigger command.

### 5.7. Channel 1 trigger ready interrupt

HW prefix: | dio_trigger_ready_1
C prefix: | TRIGGER_READY_1
Trigger: | high level

Interrupt active when time-programmable output channels accept new time trigger command.

### 5.8. Channel 2 trigger ready interrupt

HW prefix: | dio_trigger_ready_2
C prefix: | TRIGGER_READY_2
Trigger: | high level

Interrupt active when time-programmable output channels accept new time trigger command.

### 5.9. Channel 3 trigger ready interrupt

HW prefix: | dio_trigger_ready_3
C prefix: | TRIGGER_READY_3
Trigger: | high level

Interrupt active when time-programmable output channels accept new time trigger command.

### 5.10. Channel 4 trigger ready interrupt

HW prefix: | dio_trigger_ready_4
C prefix: | TRIGGER_READY_4
Trigger: | high level

Interrupt active when time-programmable output channels accept new time trigger command.