Commits · f51f4595f7d86426a4effb0cee2a00538748ddd2 · Projects / White Rabbit Trigger Distribution · Open Hardware Repository

14 Feb, 2019 6 commits
- hdl: fix memory map of SPEC150T FMC-ADC reference design · f51f4595
  Dimitris Lampridis authored Feb 14, 2019
  
  f51f4595
- hdl: improvements to reach timing closure in SPEC150T FMC-ADC reference design. Tested, works · bb32cd08
  Dimitris Lampridis authored Feb 14, 2019
  
  bb32cd08
- sim: introduce spec150t_adc ref design testbench (WIP) · 79a7656f
  Dimitris Lampridis authored Jan 30, 2019
  
  79a7656f
- hdl: introduce spec150t_adc reference design · 90d51cfa
  Dimitris Lampridis authored Jan 30, 2019
  
  90d51cfa
- hdl: move and rename old list project to wrtd_ref_svec_tdc_fd · 42c26287
  Dimitris Lampridis authored Jan 29, 2019
  
  42c26287
- sim: rename wrtd-system testbench to list · f883a9ab
  Dimitris Lampridis authored Jan 29, 2019
  
  f883a9ab
15 Oct, 2018 1 commit
- update fmc-tdc ref, reduce MT memory size. · c28b2467
  Tristan Gingold authored Oct 15, 2018
  
  c28b2467
12 Sep, 2018 1 commit
- UCF: reduce strength for oe/rd/wr/start signals to tdc fmc. · 1ab4a706
  Tristan Gingold authored Sep 12, 2018
  
  1ab4a706
11 Sep, 2018 2 commits
- Fix typo. · 99f08dd7
  Tristan Gingold authored Sep 11, 2018
  
  99f08dd7
- testbench: use $fatal in case of error. · a8d9c269
  Tristan Gingold authored Sep 11, 2018
  
  a8d9c269
04 Sep, 2018 1 commit
- hdl/syn: pack IOBs. · 12563823
  Tristan Gingold authored Sep 04, 2018
  
  12563823
22 Aug, 2018 3 commits
- testbench: now PASS/FAIL tb. · 59fd5f6f
  Tristan Gingold authored Aug 22, 2018
  
  59fd5f6f
- tb: add very simple fd monitor. · daee642c
  Tristan Gingold authored Aug 22, 2018
  
  daee642c
- testbench: improve TDC emulation. · bf9b1ed2
  Tristan Gingold authored Aug 20, 2018
  
  bf9b1ed2
17 Aug, 2018 5 commits
- CI: define SIMULATION macro. · ddda4ba1
  Tristan Gingold authored Aug 17, 2018
  
  ddda4ba1
- CI: automatically build bram files · 9874030c
  Tristan Gingold authored Aug 17, 2018
  
  9874030c
- sim: introduce WRTD driver and log message classes · b1077f0f
  Dimitris Lampridis authored Aug 17, 2018
  
  b1077f0f
- hdl: rework of timing constraints · 69f83f7c
  Dimitris Lampridis authored Aug 17, 2018
  
  69f83f7c
- hdl: add generics to initialise the instrunction RAMs of the MT CPUs · 42ee5732
  Dimitris Lampridis authored Aug 17, 2018
  
  42ee5732
01 Aug, 2018 2 commits
- hdl/sim: fix path to wrpc-sw binary for simulations · 2fafc651
  Dimitris Lampridis authored Aug 01, 2018
  
  2fafc651
- hdl/syn: embed Xilinx project options to Manifest · 806ca89c
  Dimitris Lampridis authored Aug 01, 2018
  
  806ca89c
30 Jul, 2018 1 commit
- hdl: further fine-tuning of timing constraints · b403b9ec
  Dimitris Lampridis authored Jul 30, 2018
  
  b403b9ec
27 Jul, 2018 9 commits
- hdl: further restructure and cleanup of dependencies and manifests · 9de10e18
  Dimitris Lampridis authored Jul 27, 2018
  
  9de10e18
- hdl: fix fetchto variable in Manifests · 8975076d
  Dimitris Lampridis authored Jul 27, 2018
  
  8975076d
- migrate all submodules to 'dependencies' folder at the root of the project · fc84eda0
  Dimitris Lampridis authored Jul 27, 2018
  
  fc84eda0
- hdl: update timing constraints for svec/list_tdc_fd project · 895916a8
  Dimitris Lampridis authored Jul 27, 2018
  
  895916a8
- hdl:testbench: build rmq-udp firmware before running wrtd-system testbench · c495f412
  Adam Wujek authored Jul 26, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  c495f412
- hdl:testbench: look also for a colon when greping output in Makefile · ae36bb3e
  Adam Wujek authored Jul 26, 2018
```
QuestaSim (at least version 10_5c), prints the summary after the
simulation like:
End time: 16:29:35 on Jul 26,2018, Elapsed time: 0:00:49
Errors: 1, Warnings: 9

However, the second line was recognized as a Warning and an Error.
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  ae36bb3e
- hdl:testbench: add Makefile for CI · f80bfe1a
  Adam Wujek authored Jul 24, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  f80bfe1a
- sw: reverse sender/receiver cpus in rmq_udp test used in wrtd-system testbench · 87e16c93
  Dimitris Lampridis authored Jul 27, 2018
  
  87e16c93
- hdl: fix assignment of RMQ to MT CPUs · ff70a363
  Dimitris Lampridis authored Jul 24, 2018
  
  ff70a363
24 Jul, 2018 1 commit
- hdl: bump urv core to bring in debug interface fix · 75ed93f4
  Dimitris Lampridis authored Jul 24, 2018
  
  75ed93f4
23 Jul, 2018 4 commits
- hdl/sim: update wrtd-system testbench to make use of rmq-udp test firmware · 3f5f59be
  Dimitris Lampridis authored Jul 23, 2018
  
  3f5f59be
- hdl/testbench: introduce wrtd-system testbench, work in progress · 0f641265
  Dimitris Lampridis authored Jul 23, 2018
  
  0f641265
- Add ether endpoint. · 09836380
  Tristan Gingold authored Jul 23, 2018
  
  09836380
- Use direct instantiation of MT for svec. · 8d46f8a9
  Tristan Gingold authored Jul 23, 2018
  
  8d46f8a9
20 Jul, 2018 2 commits
- hdl: new top-level with latest WRPC and MT. Missing RMQ-EP · 4a68a12e
  Dimitris Lampridis authored Jul 20, 2018
  
  4a68a12e
- hdl: make it possible to synthesize list_tdc_fd with latest wr-cores and general-cores · 545983b7
  Dimitris Lampridis authored Jul 20, 2018
  
  545983b7
04 Jul, 2018 2 commits
- connect endpoint. · 23fe4024
  Tristan Gingold authored Jul 04, 2018
  
  23fe4024
- list_tdc_fd: add mock turtle. · e6e1f0b2
  Tristan Gingold authored Jul 04, 2018
  
  e6e1f0b2