Skip to content

W
White Rabbit Trigger Distribution
Commit fc8f5fab authored by egousiou's avatar egousiou
Browse files
Options

deleted software/tools/hdl-gen

parent a06f02c1
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 0 additions and 9130 deletions
software/tools/hdl-gen/README.md deleted 100644 → 0
View file @ a06f02c1
This is a work-in-progress effort to implement a WRTD HDL generator that can take as input a
YAML-based description of a WRTD node (made of supported hardware, such as the SPEC, SVEC, FMC-ADC,
etc) and generate the top-level VHDL and necessary infrastructure to synthesize it.
**This tool is not yet done!**
software/tools/hdl-gen/builder/fmc-adc-100m14b4cha-spec/config.yaml deleted 100644 → 0
View file @ a06f02c1
repo:
"git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"
bus:
input:
"wb_adc{n}_trigin_slave"
output:
"wb_adc{n}_trigout_slave"
software/tools/hdl-gen/builder/fmc-adc-100m14b4cha-spec/repo.txt deleted 100644 → 0
View file @ a06f02c1
git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
software/tools/hdl-gen/builder/fmc-adc-100m14b4cha-spec/spec-fmc0.ucf deleted 100644 → 0
View file @ a06f02c1
# DDR (bank 3)
NET "ddr0_rzq_b" LOC = K7;
NET "ddr0_we_n_o" LOC = H2;
NET "ddr0_udqs_p_b" LOC = V2;
NET "ddr0_udqs_n_b" LOC = V1;
NET "ddr0_udm_o" LOC = P3;
NET "ddr0_reset_n_o" LOC = E3;
NET "ddr0_ras_n_o" LOC = M5;
NET "ddr0_odt_o" LOC = L6;
NET "ddr0_ldqs_p_b" LOC = N3;
NET "ddr0_ldqs_n_b" LOC = N1;
NET "ddr0_ldm_o" LOC = N4;
NET "ddr0_cke_o" LOC = F2;
NET "ddr0_ck_p_o" LOC = K4;
NET "ddr0_ck_n_o" LOC = K3;
NET "ddr0_cas_n_o" LOC = M4;
NET "ddr0_dq_b[15]" LOC = Y1;
NET "ddr0_dq_b[14]" LOC = Y2;
NET "ddr0_dq_b[13]" LOC = W1;
NET "ddr0_dq_b[12]" LOC = W3;
NET "ddr0_dq_b[11]" LOC = U1;
NET "ddr0_dq_b[10]" LOC = U3;
NET "ddr0_dq_b[9]" LOC = T1;
NET "ddr0_dq_b[8]" LOC = T2;
NET "ddr0_dq_b[7]" LOC = M1;
NET "ddr0_dq_b[6]" LOC = M2;
NET "ddr0_dq_b[5]" LOC = L1;
NET "ddr0_dq_b[4]" LOC = L3;
NET "ddr0_dq_b[3]" LOC = P1;
NET "ddr0_dq_b[2]" LOC = P2;
NET "ddr0_dq_b[1]" LOC = R1;
NET "ddr0_dq_b[0]" LOC = R3;
NET "ddr0_ba_o[2]" LOC = H1;
NET "ddr0_ba_o[1]" LOC = J1;
NET "ddr0_ba_o[0]" LOC = J3;
NET "ddr0_a_o[13]" LOC = J6;
NET "ddr0_a_o[12]" LOC = F1;
NET "ddr0_a_o[11]" LOC = E1;
NET "ddr0_a_o[10]" LOC = J4;
NET "ddr0_a_o[9]" LOC = G1;
NET "ddr0_a_o[8]" LOC = G3;
NET "ddr0_a_o[7]" LOC = K6;
NET "ddr0_a_o[6]" LOC = L4;
NET "ddr0_a_o[5]" LOC = M3;
NET "ddr0_a_o[4]" LOC = H3;
NET "ddr0_a_o[3]" LOC = M6;
NET "ddr0_a_o[2]" LOC = K5;
NET "ddr0_a_o[1]" LOC = K1;
NET "ddr0_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IN_TERM = NONE;
NET "ddr0_ldqs_p_b" IN_TERM = NONE;
NET "ddr0_ldqs_n_b" IN_TERM = NONE;
NET "ddr0_udqs_p_b" IN_TERM = NONE;
NET "ddr0_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# FMC slot
#----------------------------------------
NET "fmc0_adc_ext_trigger_n_i" LOC = AB13;
NET "fmc0_adc_ext_trigger_p_i" LOC = Y13;
# dco_p and dco_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "fmc0_adc_dco_n_i" LOC = AB11;
NET "fmc0_adc_dco_p_i" LOC = Y11;
# fr_p and fr_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "fmc0_adc_fr_n_i" LOC = AB12;
NET "fmc0_adc_fr_p_i" LOC = AA12;
NET "fmc0_adc_outa_n_i[0]" LOC = AB4;
NET "fmc0_adc_outa_p_i[0]" LOC = AA4;
NET "fmc0_adc_outb_n_i[0]" LOC = W11;
NET "fmc0_adc_outb_p_i[0]" LOC = V11;
NET "fmc0_adc_outa_n_i[1]" LOC = Y12;
NET "fmc0_adc_outa_p_i[1]" LOC = W12;
NET "fmc0_adc_outb_n_i[1]" LOC = AB9;
NET "fmc0_adc_outb_p_i[1]" LOC = Y9;
NET "fmc0_adc_outa_n_i[2]" LOC = AB8;
NET "fmc0_adc_outa_p_i[2]" LOC = AA8;
NET "fmc0_adc_outb_n_i[2]" LOC = AB7;
NET "fmc0_adc_outb_p_i[2]" LOC = Y7;
NET "fmc0_adc_outa_n_i[3]" LOC = V9;
NET "fmc0_adc_outa_p_i[3]" LOC = U9;
NET "fmc0_adc_outb_n_i[3]" LOC = AB6;
NET "fmc0_adc_outb_p_i[3]" LOC = AA6;
NET "fmc0_adc_spi_din_i" LOC = T15;
NET "fmc0_adc_spi_dout_o" LOC = C18;
NET "fmc0_adc_spi_sck_o" LOC = D17;
NET "fmc0_adc_spi_cs_adc_n_o" LOC = V17;
NET "fmc0_adc_spi_cs_dac1_n_o" LOC = B20;
NET "fmc0_adc_spi_cs_dac2_n_o" LOC = A20;
NET "fmc0_adc_spi_cs_dac3_n_o" LOC = C19;
NET "fmc0_adc_spi_cs_dac4_n_o" LOC = A19;
NET "fmc0_adc_gpio_dac_clr_n_o" LOC = W18;
NET "fmc0_adc_gpio_led_acq_o" LOC = W15;
NET "fmc0_adc_gpio_led_trig_o" LOC = Y16;
NET "fmc0_adc_gpio_ssr_ch1_o[0]" LOC = Y17;
NET "fmc0_adc_gpio_ssr_ch1_o[1]" LOC = AB17;
NET "fmc0_adc_gpio_ssr_ch1_o[2]" LOC = AB18;
NET "fmc0_adc_gpio_ssr_ch1_o[3]" LOC = U15;
NET "fmc0_adc_gpio_ssr_ch1_o[4]" LOC = W14;
NET "fmc0_adc_gpio_ssr_ch1_o[5]" LOC = Y14;
NET "fmc0_adc_gpio_ssr_ch1_o[6]" LOC = W17;
NET "fmc0_adc_gpio_ssr_ch2_o[0]" LOC = R11;
NET "fmc0_adc_gpio_ssr_ch2_o[1]" LOC = AB15;
NET "fmc0_adc_gpio_ssr_ch2_o[2]" LOC = R13;
NET "fmc0_adc_gpio_ssr_ch2_o[3]" LOC = T14;
NET "fmc0_adc_gpio_ssr_ch2_o[4]" LOC = V13;
NET "fmc0_adc_gpio_ssr_ch2_o[5]" LOC = AA18;
NET "fmc0_adc_gpio_ssr_ch2_o[6]" LOC = W13;
NET "fmc0_adc_gpio_ssr_ch3_o[0]" LOC = R9;
NET "fmc0_adc_gpio_ssr_ch3_o[1]" LOC = R8;
NET "fmc0_adc_gpio_ssr_ch3_o[2]" LOC = T10;
NET "fmc0_adc_gpio_ssr_ch3_o[3]" LOC = U10;
NET "fmc0_adc_gpio_ssr_ch3_o[4]" LOC = W10;
NET "fmc0_adc_gpio_ssr_ch3_o[5]" LOC = Y10;
NET "fmc0_adc_gpio_ssr_ch3_o[6]" LOC = T11;
NET "fmc0_adc_gpio_ssr_ch4_o[0]" LOC = W6;
NET "fmc0_adc_gpio_ssr_ch4_o[1]" LOC = Y6;
NET "fmc0_adc_gpio_ssr_ch4_o[2]" LOC = V7;
NET "fmc0_adc_gpio_ssr_ch4_o[3]" LOC = W8;
NET "fmc0_adc_gpio_ssr_ch4_o[4]" LOC = T8;
NET "fmc0_adc_gpio_ssr_ch4_o[5]" LOC = Y5;
NET "fmc0_adc_gpio_ssr_ch4_o[6]" LOC = U8;
NET "fmc0_adc_gpio_si570_oe_o" LOC = AB5;
NET "fmc0_adc_si570_scl_b" LOC = U12;
NET "fmc0_adc_si570_sda_b" LOC = T12;
NET "fmc0_adc_one_wire_b" LOC = Y18;
# IO standards
NET "fmc0_adc_ext_trigger_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_dco_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_fr_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_spi_din_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_dac?_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr0_ctrl_bank/*/c?_pll_lock" TIG;
NET "cmp_ddr0_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "ddr0_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "cmp_ddr0_ctrl_bank/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank3_clk;
TIMEGRP "ddr0_clk" = "ddr0_clk_333m" "ddr0_bank3_clk";
TIMEGRP "ddr0_sync_ffs" = "sync_ffs" EXCEPT "ddr0_clk";
TIMEGRP "fmc0_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMESPEC TS_ddr0_sync_ffs = FROM ddr0_clk TO "ddr0_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMEGRP "ddr0_sync_reg" = "sync_reg" EXCEPT "ddr0_clk";
TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY;
software/tools/hdl-gen/builder/fmc-adc-100m14b4cha-svec/config.yaml deleted 100644 → 0
View file @ a06f02c1
repo:
"git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git"
bus:
input:
"wb_adc{n}_trigin_slave"
output:
"wb_adc{n}_trigout_slave"
software/tools/hdl-gen/builder/fmc-adc-100m14b4cha-svec/repo.txt deleted 100644 → 0
View file @ a06f02c1
git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
software/tools/hdl-gen/builder/fmc-adc-100m14b4cha-svec/svec-fmc0.ucf deleted 100644 → 0
View file @ a06f02c1
# DDR0 (bank 4)
NET "ddr0_rzq_b" LOC = L7;
NET "ddr0_we_n_o" LOC = F4;
NET "ddr0_udqs_p_b" LOC = K2;
NET "ddr0_udqs_n_b" LOC = K1;
NET "ddr0_udm_o" LOC = K4;
NET "ddr0_reset_n_o" LOC = G5;
NET "ddr0_ras_n_o" LOC = C1;
NET "ddr0_odt_o" LOC = E4;
NET "ddr0_ldqs_p_b" LOC = J5;
NET "ddr0_ldqs_n_b" LOC = J4;
NET "ddr0_ldm_o" LOC = K3;
NET "ddr0_cke_o" LOC = C4;
NET "ddr0_ck_p_o" LOC = E3;
NET "ddr0_ck_n_o" LOC = E1;
NET "ddr0_cas_n_o" LOC = B1;
NET "ddr0_dq_b[15]" LOC = M1;
NET "ddr0_dq_b[14]" LOC = M2;
NET "ddr0_dq_b[13]" LOC = L1;
NET "ddr0_dq_b[12]" LOC = L3;
NET "ddr0_dq_b[11]" LOC = L4;
NET "ddr0_dq_b[10]" LOC = L5;
NET "ddr0_dq_b[9]" LOC = M3;
NET "ddr0_dq_b[8]" LOC = M4;
NET "ddr0_dq_b[7]" LOC = H1;
NET "ddr0_dq_b[6]" LOC = H2;
NET "ddr0_dq_b[5]" LOC = G1;
NET "ddr0_dq_b[4]" LOC = G3;
NET "ddr0_dq_b[3]" LOC = J1;
NET "ddr0_dq_b[2]" LOC = J3;
NET "ddr0_dq_b[1]" LOC = H3;
NET "ddr0_dq_b[0]" LOC = H4;
NET "ddr0_ba_o[2]" LOC = F3;
NET "ddr0_ba_o[1]" LOC = D1;
NET "ddr0_ba_o[0]" LOC = D2;
NET "ddr0_a_o[13]" LOC = B5;
NET "ddr0_a_o[12]" LOC = A4;
NET "ddr0_a_o[11]" LOC = G4;
NET "ddr0_a_o[10]" LOC = D5;
NET "ddr0_a_o[9]" LOC = A2;
NET "ddr0_a_o[8]" LOC = B2;
NET "ddr0_a_o[7]" LOC = B3;
NET "ddr0_a_o[6]" LOC = F1;
NET "ddr0_a_o[5]" LOC = F2;
NET "ddr0_a_o[4]" LOC = C5;
NET "ddr0_a_o[3]" LOC = E5;
NET "ddr0_a_o[2]" LOC = A3;
NET "ddr0_a_o[1]" LOC = D3;
NET "ddr0_a_o[0]" LOC = D4;
# DDR IO standards and terminations
NET "ddr0_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr0_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr0_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr0_dq_b[*]" IN_TERM = NONE;
NET "ddr0_ldqs_p_b" IN_TERM = NONE;
NET "ddr0_ldqs_n_b" IN_TERM = NONE;
NET "ddr0_udqs_p_b" IN_TERM = NONE;
NET "ddr0_udqs_n_b" IN_TERM = NONE;
# FMC0
NET "fmc0_adc_ext_trigger_n_i" LOC = "A15";
NET "fmc0_adc_ext_trigger_p_i" LOC = "B15";
NET "fmc0_adc_dco_n_i" LOC = "A16";
NET "fmc0_adc_dco_p_i" LOC = "C16";
NET "fmc0_adc_fr_n_i" LOC = "G21";
NET "fmc0_adc_fr_p_i" LOC = "H21";
NET "fmc0_adc_outa_n_i[0]" LOC = "E17";
NET "fmc0_adc_outa_p_i[0]" LOC = "F17";
NET "fmc0_adc_outb_n_i[0]" LOC = "G16";
NET "fmc0_adc_outb_p_i[0]" LOC = "H16";
NET "fmc0_adc_outa_n_i[1]" LOC = "E19";
NET "fmc0_adc_outa_p_i[1]" LOC = "F19";
NET "fmc0_adc_outb_n_i[1]" LOC = "F18";
NET "fmc0_adc_outb_p_i[1]" LOC = "G18";
NET "fmc0_adc_outa_n_i[2]" LOC = "K21";
NET "fmc0_adc_outa_p_i[2]" LOC = "L21";
NET "fmc0_adc_outb_n_i[2]" LOC = "L20";
NET "fmc0_adc_outb_p_i[2]" LOC = "M20";
NET "fmc0_adc_outa_n_i[3]" LOC = "F22";
NET "fmc0_adc_outa_p_i[3]" LOC = "G22";
NET "fmc0_adc_outb_n_i[3]" LOC = "L19";
NET "fmc0_adc_outb_p_i[3]" LOC = "M19";
NET "fmc0_adc_spi_din_i" LOC = "F11";
NET "fmc0_adc_spi_dout_o" LOC = "K11";
NET "fmc0_adc_spi_sck_o" LOC = "L11";
NET "fmc0_adc_spi_cs_adc_n_o" LOC = "J13";
NET "fmc0_adc_spi_cs_dac1_n_o" LOC = "H11";
NET "fmc0_adc_spi_cs_dac2_n_o" LOC = "G11";
NET "fmc0_adc_spi_cs_dac3_n_o" LOC = "J12";
NET "fmc0_adc_spi_cs_dac4_n_o" LOC = "H12";
NET "fmc0_adc_gpio_dac_clr_n_o" LOC = "H13";
NET "fmc0_adc_gpio_led_acq_o" LOC = "K12";
NET "fmc0_adc_gpio_led_trig_o" LOC = "L12";
NET "fmc0_adc_gpio_ssr_ch1_o[0]" LOC = "L14";
NET "fmc0_adc_gpio_ssr_ch1_o[1]" LOC = "K14";
NET "fmc0_adc_gpio_ssr_ch1_o[2]" LOC = "L13";
NET "fmc0_adc_gpio_ssr_ch1_o[3]" LOC = "E11";
NET "fmc0_adc_gpio_ssr_ch1_o[4]" LOC = "G10";
NET "fmc0_adc_gpio_ssr_ch1_o[5]" LOC = "F10";
NET "fmc0_adc_gpio_ssr_ch1_o[6]" LOC = "F9";
NET "fmc0_adc_gpio_ssr_ch2_o[0]" LOC = "F15";
NET "fmc0_adc_gpio_ssr_ch2_o[1]" LOC = "F14";
NET "fmc0_adc_gpio_ssr_ch2_o[2]" LOC = "F13";
NET "fmc0_adc_gpio_ssr_ch2_o[3]" LOC = "E13";
NET "fmc0_adc_gpio_ssr_ch2_o[4]" LOC = "G12";
NET "fmc0_adc_gpio_ssr_ch2_o[5]" LOC = "M13";
NET "fmc0_adc_gpio_ssr_ch2_o[6]" LOC = "F12";
NET "fmc0_adc_gpio_ssr_ch3_o[0]" LOC = "F23";
NET "fmc0_adc_gpio_ssr_ch3_o[1]" LOC = "E23";
NET "fmc0_adc_gpio_ssr_ch3_o[2]" LOC = "F21";
NET "fmc0_adc_gpio_ssr_ch3_o[3]" LOC = "E21";
NET "fmc0_adc_gpio_ssr_ch3_o[4]" LOC = "G20";
NET "fmc0_adc_gpio_ssr_ch3_o[5]" LOC = "F20";
NET "fmc0_adc_gpio_ssr_ch3_o[6]" LOC = "E15";
NET "fmc0_adc_gpio_ssr_ch4_o[0]" LOC = "J22";
NET "fmc0_adc_gpio_ssr_ch4_o[1]" LOC = "H22";
NET "fmc0_adc_gpio_ssr_ch4_o[2]" LOC = "E25";
NET "fmc0_adc_gpio_ssr_ch4_o[3]" LOC = "D25";
NET "fmc0_adc_gpio_ssr_ch4_o[4]" LOC = "D24";
NET "fmc0_adc_gpio_ssr_ch4_o[5]" LOC = "B25";
NET "fmc0_adc_gpio_ssr_ch4_o[6]" LOC = "C24";
NET "fmc0_adc_gpio_si570_oe_o" LOC = "A25";
NET "fmc0_adc_si570_scl_b" LOC = "H14";
NET "fmc0_adc_si570_sda_b" LOC = "J14";
NET "fmc0_adc_one_wire_b" LOC = "E9";
# IO standards
NET "fmc0_adc_ext_trigger_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_dco_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_fr_?_i" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_out?_?_i[*]" IOSTANDARD = "LVDS_25";
NET "fmc0_adc_spi_din_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_spi_cs_dac?_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_ssr_ch?_o[*]" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
#----------------------------------------
# Clocks
#----------------------------------------
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "cmp_ddr0_ctrl_bank/*/c?_pll_lock" TIG;
NET "cmp_ddr0_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#ERR NET "cmp_ddr0_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "rst_ddr_333m_n" TPTHRU = ddr0_rst;
TIMESPEC TS_ddr0_rst_tig = FROM FFS THRU ddr0_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs0_clk;
NET "cmp_ddr0_ctrl_bank/*/memc4_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_bank4_clk;
TIMEGRP "ddr0_clk" = "ddr_clk_333m" "ddr_bank4_clk";
TIMEGRP "ddr0_sync_ffs" = "sync_ffs" EXCEPT "ddr0_clk";
TIMEGRP "adc0_sync_ffs" = "sync_ffs" EXCEPT "fs0_clk";
TIMESPEC TS_ddr0_sync_ffs = FROM ddr0_clk TO "ddr0_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG;
TIMEGRP "ddr0_sync_reg" = "sync_reg" EXCEPT "ddr0_clk";
TIMEGRP "adc0_sync_reg" = "sync_reg" EXCEPT "fs0_clk";
TIMESPEC TS_ddr0_sync_reg = FROM ddr0_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc0_sync_reg = FROM fs0_clk TO "adc0_sync_reg" 10ns DATAPATHONLY;
software/tools/hdl-gen/builder/fmc-adc-100m14b4cha-svec/svec-fmc1.ucf deleted 100644 → 0
View file @ a06f02c1
# DDR1 (bank 5)
NET "ddr_rzq_b[1]" LOC = G25;
NET "ddr_we_n_o[1]" LOC = E26;
NET "ddr_udqs_p_b[1]" LOC = K28;
NET "ddr_udqs_n_b[1]" LOC = K30;
NET "ddr_udm_o[1]" LOC = J27;
NET "ddr_reset_n_o[1]" LOC = C26;
NET "ddr_ras_n_o[1]" LOC = K26;
NET "ddr_odt_o[1]" LOC = E30;
NET "ddr_ldqs_p_b[1]" LOC = J29;
NET "ddr_ldqs_n_b[1]" LOC = J30;
NET "ddr_ldm_o[1]" LOC = J28;
NET "ddr_cke_o[1]" LOC = B29;
NET "ddr_ck_p_o[1]" LOC = E27;
NET "ddr_ck_n_o[1]" LOC = E28;
NET "ddr_cas_n_o[1]" LOC = K27;
NET "ddr_dq_b[31]" LOC = M30;
NET "ddr_dq_b[30]" LOC = M28;
NET "ddr_dq_b[29]" LOC = M27;
NET "ddr_dq_b[28]" LOC = M26;
NET "ddr_dq_b[27]" LOC = L30;
NET "ddr_dq_b[26]" LOC = L29;
NET "ddr_dq_b[25]" LOC = L28;
NET "ddr_dq_b[24]" LOC = L27;
NET "ddr_dq_b[23]" LOC = F30;
NET "ddr_dq_b[22]" LOC = F28;
NET "ddr_dq_b[21]" LOC = G28;
NET "ddr_dq_b[20]" LOC = G27;
NET "ddr_dq_b[19]" LOC = G30;
NET "ddr_dq_b[18]" LOC = G29;
NET "ddr_dq_b[17]" LOC = H30;
NET "ddr_dq_b[16]" LOC = H28;
NET "ddr_ba_o[5]" LOC = D26;
NET "ddr_ba_o[4]" LOC = C27;
NET "ddr_ba_o[3]" LOC = D27;
NET "ddr_a_o[27]" LOC = A28;
NET "ddr_a_o[26]" LOC = B30;
NET "ddr_a_o[25]" LOC = A26;
NET "ddr_a_o[24]" LOC = F26;
NET "ddr_a_o[23]" LOC = A27;
NET "ddr_a_o[22]" LOC = B27;
NET "ddr_a_o[21]" LOC = C29;
NET "ddr_a_o[20]" LOC = H27;
NET "ddr_a_o[19]" LOC = H26;
NET "ddr_a_o[18]" LOC = F27;
NET "ddr_a_o[17]" LOC = E29;
NET "ddr_a_o[16]" LOC = C30;
NET "ddr_a_o[15]" LOC = D30;
NET "ddr_a_o[14]" LOC = D28;
software/tools/hdl-gen/builder/fmc-delay-1ns-8cha/repo.txt deleted 100644 → 0
View file @ a06f02c1
git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git
software/tools/hdl-gen/builder/fmc-delay-1ns-8cha/svec-fmc0.ucf deleted 100644 → 0
View file @ a06f02c1
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 0
NET "fmc0_fd_clk_ref_p_i" LOC = "E16";
NET "fmc0_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_clk_ref_n_i" LOC = "D16";
NET "fmc0_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_p_i" LOC = "H15";
NET "fmc0_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_tdc_start_n_i" LOC = "G15";
NET "fmc0_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_fd_delay_len_o[3]" LOC = "G10";
NET "fmc0_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[2]" LOC = "F10";
NET "fmc0_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[1]" LOC = "E9";
NET "fmc0_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_len_o[0]" LOC = "F9";
NET "fmc0_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_pulse_o[3]" LOC = "F12";
NET "fmc0_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[1]" LOC = "E11";
NET "fmc0_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[2]" LOC = "G12";
NET "fmc0_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_pulse_o[0]" LOC = "F11";
NET "fmc0_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" LOC = "J12";
NET "fmc0_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[1]" LOC = "H11";
NET "fmc0_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[7]" LOC = "L11";
NET "fmc0_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[5]" LOC = "J13";
NET "fmc0_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[9]" LOC = "L12";
NET "fmc0_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc0_fd_spi_mosi_o" LOC = "M13";
NET "fmc0_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_sclk_o" LOC = "L14";
NET "fmc0_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_oe_n_o" LOC = "M15";
NET "fmc0_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_start_dis_o" LOC = "F13";
NET "fmc0_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_gpio_n_o" LOC = "F15";
NET "fmc0_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_cal_pulse_o" LOC = "G14";
NET "fmc0_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_clk_o" LOC = "J14";
NET "fmc0_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_wr_n_o" LOC = "B15";
NET "fmc0_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_alutrigger_o" LOC = "F19";
NET "fmc0_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_led_trig_o" LOC = "H16";
NET "fmc0_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[26]" LOC = "F17";
NET "fmc0_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[24]" LOC = "G18";
NET "fmc0_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[20]" LOC = "F21";
NET "fmc0_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[22]" LOC = "G20";
NET "fmc0_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[18]" LOC = "L21";
NET "fmc0_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[16]" LOC = "M20";
NET "fmc0_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[10]" LOC = "F23";
NET "fmc0_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[14]" LOC = "G22";
NET "fmc0_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[8]" LOC = "B25";
NET "fmc0_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[12]" LOC = "M19";
NET "fmc0_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[3]" LOC = "D24";
NET "fmc0_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[5]" LOC = "E25";
NET "fmc0_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[7]" LOC = "J22";
NET "fmc0_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[2]" LOC = "H21";
NET "fmc0_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_trig_a_i" LOC = "C16";
NET "fmc0_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" LOC = "H12";
NET "fmc0_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[0]" LOC = "G11";
NET "fmc0_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[6]" LOC = "K11";
NET "fmc0_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[4]" LOC = "H13";
NET "fmc0_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc0_fd_delay_val_o[8]" LOC = "K12";
NET "fmc0_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc0_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc0_fd_spi_miso_i" LOC = "L13";
NET "fmc0_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_pll_n_o" LOC = "K14";
NET "fmc0_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_spi_cs_dac_n_o" LOC = "K15";
NET "fmc0_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_stop_dis_o" LOC = "E13";
NET "fmc0_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_ext_rst_n_o" LOC = "E15";
NET "fmc0_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_pll_status_i" LOC = "F14";
NET "fmc0_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_out_i" LOC = "H14";
NET "fmc0_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_rd_n_o" LOC = "A15";
NET "fmc0_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_emptyf_i" LOC = "E19";
NET "fmc0_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_onewire_b" LOC = "G16";
NET "fmc0_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[27]" LOC = "E17";
NET "fmc0_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[25]" LOC = "F18";
NET "fmc0_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[21]" LOC = "E21";
NET "fmc0_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[23]" LOC = "F20";
NET "fmc0_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[19]" LOC = "K21";
NET "fmc0_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[17]" LOC = "L20";
NET "fmc0_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[11]" LOC = "E23";
NET "fmc0_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[15]" LOC = "F22";
NET "fmc0_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[9]" LOC = "A25";
NET "fmc0_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[13]" LOC = "L19";
NET "fmc0_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[1]" LOC = "C24";
NET "fmc0_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[4]" LOC = "D25";
NET "fmc0_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[6]" LOC = "H22";
NET "fmc0_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_tdc_d_b[0]" LOC = "G21";
NET "fmc0_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_fd_dmtd_fb_in_i" LOC = "A16";
NET "fmc0_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc0_clk_125m" TNM_NET = fmc0_clk_125m;
TIMEGRP "fmc0_sync"="synchronizers" EXCEPT "fmc0_clk_125m";
TIMESPEC TS_fmc0_sync_ffs = FROM fmc0_clk_125m TO "fmc0_sync" 20ns DATAPATHONLY;
software/tools/hdl-gen/builder/fmc-delay-1ns-8cha/svec-fmc1.ucf deleted 100644 → 0
View file @ a06f02c1
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fmc1_fd_clk_ref_p_i" LOC = "AH16";
NET "fmc1_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_clk_ref_n_i" LOC = "AK16";
NET "fmc1_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_p_i" LOC = "AF16";
NET "fmc1_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_n_i" LOC = "AG16";
NET "fmc1_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_delay_len_o[3]" LOC = "AB21";
NET "fmc1_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[2]" LOC = "AC21";
NET "fmc1_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[1]" LOC = "AD24";
NET "fmc1_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[0]" LOC = "AC24";
NET "fmc1_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_pulse_o[3]" LOC = "AE22";
NET "fmc1_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[1]" LOC = "AD17";
NET "fmc1_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[2]" LOC = "AD22";
NET "fmc1_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[0]" LOC = "AB17";
NET "fmc1_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" LOC = "AA19";
NET "fmc1_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[1]" LOC = "W19";
NET "fmc1_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[7]" LOC = "Y21";
NET "fmc1_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[5]" LOC = "W20";
NET "fmc1_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[9]" LOC = "AA22";
NET "fmc1_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc1_fd_spi_mosi_o" LOC = "AB20";
NET "fmc1_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_sclk_o" LOC = "AC19";
NET "fmc1_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_oe_n_o" LOC = "AF25";
NET "fmc1_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_start_dis_o" LOC = "AE24";
NET "fmc1_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_gpio_n_o" LOC = "AE19";
NET "fmc1_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_cal_pulse_o" LOC = "AE23";
NET "fmc1_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_clk_o" LOC = "AE21";
NET "fmc1_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_wr_n_o" LOC = "AC16";
NET "fmc1_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_alutrigger_o" LOC = "AB14";
NET "fmc1_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_led_trig_o" LOC = "Y17";
NET "fmc1_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[26]" LOC = "Y15";
NET "fmc1_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[24]" LOC = "AC15";
NET "fmc1_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[20]" LOC = "AE15";
NET "fmc1_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[22]" LOC = "Y16";
NET "fmc1_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[18]" LOC = "Y14";
NET "fmc1_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[16]" LOC = "W14";
NET "fmc1_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[10]" LOC = "AB12";
NET "fmc1_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[14]" LOC = "AD12";
NET "fmc1_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[8]" LOC = "AD10";
NET "fmc1_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[12]" LOC = "AE11";
NET "fmc1_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[3]" LOC = "AJ15";
NET "fmc1_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[5]" LOC = "AE13";
NET "fmc1_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[7]" LOC = "AC11";
NET "fmc1_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[2]" LOC = "AG8";
NET "fmc1_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_trig_a_i" LOC = "AJ17";
NET "fmc1_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" LOC = "AB19";
NET "fmc1_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[0]" LOC = "Y19";
NET "fmc1_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[6]" LOC = "AA21";
NET "fmc1_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[4]" LOC = "Y20";
NET "fmc1_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[8]" LOC = "AC22";
NET "fmc1_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc1_fd_spi_miso_i" LOC = "AC20";
NET "fmc1_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_pll_n_o" LOC = "AD19";
NET "fmc1_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_dac_n_o" LOC = "AG25";
NET "fmc1_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_stop_dis_o" LOC = "AF24";
NET "fmc1_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_ext_rst_n_o" LOC = "AF19";
NET "fmc1_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_pll_status_i" LOC = "AF23";
NET "fmc1_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_out_i" LOC = "AF21";
NET "fmc1_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_rd_n_o" LOC = "AD16";
NET "fmc1_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_emptyf_i" LOC = "AC14";
NET "fmc1_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_onewire_b" LOC = "AA17";
NET "fmc1_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[27]" LOC = "AA15";
NET "fmc1_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[25]" LOC = "AD15";
NET "fmc1_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[21]" LOC = "AF15";
NET "fmc1_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[23]" LOC = "AB16";
NET "fmc1_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[19]" LOC = "AA14";
NET "fmc1_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[17]" LOC = "Y13";
NET "fmc1_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[11]" LOC = "AC12";
NET "fmc1_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[15]" LOC = "AE12";
NET "fmc1_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[9]" LOC = "AE10";
NET "fmc1_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[13]" LOC = "AF11";
NET "fmc1_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[1]" LOC = "AK15";
NET "fmc1_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[4]" LOC = "AF13";
NET "fmc1_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[6]" LOC = "AD11";
NET "fmc1_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[0]" LOC = "AH8";
NET "fmc1_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_in_i" LOC = "AK17";
NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# All input clocks
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
NET "fmc1_clk_125m" TNM_NET = fmc1_clk_125m;
TIMEGRP "fmc1_sync"="synchronizers" EXCEPT "fmc1_clk_125m";
TIMESPEC TS_fmc1_sync_ffs = FROM fmc1_clk_125m TO "fmc1_sync" 20ns DATAPATHONLY;
software/tools/hdl-gen/builder/fmc-delay-1ns-8cha/top.vhd deleted 100644 → 0
View file @ a06f02c1
[use]
use work.fine_delay_pkg.all;
[ports]
---------------------------------------------------------------------------
-- FMC slot {n} pins (FDELAY mezzanine)
---------------------------------------------------------------------------
fmc{n}_fd_tdc_start_p_i : in std_logic;
fmc{n}_fd_tdc_start_n_i : in std_logic;
fmc{n}_fd_clk_ref_p_i : in std_logic;
fmc{n}_fd_clk_ref_n_i : in std_logic;
fmc{n}_fd_trig_a_i : in std_logic;
fmc{n}_fd_tdc_cal_pulse_o : out std_logic;
fmc{n}_fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fmc{n}_fd_tdc_emptyf_i : in std_logic;
fmc{n}_fd_tdc_alutrigger_o : out std_logic;
fmc{n}_fd_tdc_wr_n_o : out std_logic;
fmc{n}_fd_tdc_rd_n_o : out std_logic;
fmc{n}_fd_tdc_oe_n_o : out std_logic;
fmc{n}_fd_led_trig_o : out std_logic;
fmc{n}_fd_tdc_start_dis_o : out std_logic;
fmc{n}_fd_tdc_stop_dis_o : out std_logic;
fmc{n}_fd_spi_cs_dac_n_o : out std_logic;
fmc{n}_fd_spi_cs_pll_n_o : out std_logic;
fmc{n}_fd_spi_cs_gpio_n_o : out std_logic;
fmc{n}_fd_spi_sclk_o : out std_logic;
fmc{n}_fd_spi_mosi_o : out std_logic;
fmc{n}_fd_spi_miso_i : in std_logic;
fmc{n}_fd_delay_len_o : out std_logic_vector(3 downto 0);
fmc{n}_fd_delay_val_o : out std_logic_vector(9 downto 0);
fmc{n}_fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc{n}_fd_dmtd_clk_o : out std_logic;
fmc{n}_fd_dmtd_fb_in_i : in std_logic;
fmc{n}_fd_dmtd_fb_out_i : in std_logic;
fmc{n}_fd_pll_status_i : in std_logic;
fmc{n}_fd_ext_rst_n_o : out std_logic;
fmc{n}_fd_onewire_b : inout std_logic;
[sdb-decl]
[sdb-layout]
c_WB_SLAVE_FMC{n} => f_sdb_embed_device(c_FD_SDB_DEVICE, x"{addr}"),
[decls]
-- Muxed Host and MT WB interface to FMC{n}
signal fmc{n}_mux_wb_out : t_wishbone_master_out;
signal fmc{n}_mux_wb_in : t_wishbone_master_in;
-- Misc FMC signals
signal fmc{n}_fd_tdc_start : std_logic;
signal ddr{n}_pll_reset : std_logic;
signal ddr{n}_pll_locked : std_logic;
signal fmc{n}_fd_pll_status : std_logic;
signal fmc{n}_fd_tdc_data_out : std_logic_vector(27 downto 0);
signal fmc{n}_fd_tdc_data_in : std_logic_vector(27 downto 0);
signal fmc{n}_fd_tdc_data_oe : std_logic;
signal fmc{n}_fd_owr_en, fmc{n}_fd_owr_in : std_logic;
signal fmc{n}_fd_scl_in : std_logic;
signal fmc{n}_fd_sda_in : std_logic;
signal fmc{n}_clk_125m_180 : std_logic;
[body]
-----------------------------------------------------------------------------
-- FMC FDELAY (SVEC slot #{n})
-----------------------------------------------------------------------------
cmp_fd_tdc_start{n} : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE)
port map (
O => fmc{n}_fd_tdc_start,
I => fmc{n}_fd_tdc_start_p_i,
IB => fmc{n}_fd_tdc_start_n_i);
U_DDR_PLL1 : entity work.fd_ddr_pll
port map (
RST => ddr{n}_pll_reset,
LOCKED => ddr{n}_pll_locked,
CLK_IN1_P => fmc{n}_fd_clk_ref_p_i,
CLK_IN1_N => fmc{n}_fd_clk_ref_n_i,
CLK_OUT1 => fmc{n}_clk_125m,
CLK_OUT2 => fmc{n}_clk_125m_180);
ddr{n}_pll_reset <= not fmc{n}_fd_pll_status_i;
fmc{n}_fd_pll_status <= fmc{n}_fd_pll_status_i and ddr{n}_pll_locked;
U_FineDelay_Core{n} : fine_delay_core
generic map (
g_with_wr_core => TRUE,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => fmc{n}_clk_125m,
clk_ref_180_i => fmc{n}_clk_125m_180,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => '0',
rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open,
dcm_locked_i => ddr{n}_pll_locked,
trig_a_i => fmc{n}_fd_trig_a_i,
tdc_cal_pulse_o => fmc{n}_fd_tdc_cal_pulse_o,
tdc_start_i => fmc{n}_fd_tdc_start,
dmtd_fb_in_i => fmc{n}_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fmc{n}_fd_dmtd_fb_out_i,
dmtd_samp_o => fmc{n}_fd_dmtd_clk_o,
led_trig_o => fmc{n}_fd_led_trig_o,
ext_rst_n_o => fmc{n}_fd_ext_rst_n_o,
pll_status_i => fmc{n}_fd_pll_status,
acam_d_o => fmc{n}_fd_tdc_data_out,
acam_d_i => fmc{n}_fd_tdc_data_in,
acam_d_oen_o => fmc{n}_fd_tdc_data_oe,
acam_emptyf_i => fmc{n}_fd_tdc_emptyf_i,
acam_alutrigger_o => fmc{n}_fd_tdc_alutrigger_o,
acam_wr_n_o => fmc{n}_fd_tdc_wr_n_o,
acam_rd_n_o => fmc{n}_fd_tdc_rd_n_o,
acam_start_dis_o => fmc{n}_fd_tdc_start_dis_o,
acam_stop_dis_o => fmc{n}_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fmc{n}_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fmc{n}_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fmc{n}_fd_spi_cs_gpio_n_o,
spi_sclk_o => fmc{n}_fd_spi_sclk_o,
spi_mosi_o => fmc{n}_fd_spi_mosi_o,
spi_miso_i => fmc{n}_fd_spi_miso_i,
delay_len_o => fmc{n}_fd_delay_len_o,
delay_val_o => fmc{n}_fd_delay_val_o,
delay_pulse_o => fmc{n}_fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en({n}),
tm_clk_aux_locked_i => tm_clk_aux_locked({n}),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr({n}),
owr_en_o => fmc{n}_fd_owr_en,
owr_i => fmc{n}_fd_owr_in,
i2c_scl_oen_o => fmc{n}_scl_out,
i2c_scl_i => fmc{n}_fd_scl_in,
i2c_sda_oen_o => fmc{n}_sda_out,
i2c_sda_i => fmc{n}_fd_sda_in,
fmc_present_n_i => fmc{n}_prsntm2c_n_i,
wb_adr_i => fmc{n}_mux_wb_out.adr,
wb_dat_i => fmc{n}_mux_wb_out.dat,
wb_dat_o => fmc{n}_mux_wb_in.dat,
wb_sel_i => fmc{n}_mux_wb_out.sel,
wb_cyc_i => fmc{n}_mux_wb_out.cyc,
wb_stb_i => fmc{n}_mux_wb_out.stb,
wb_we_i => fmc{n}_mux_wb_out.we,
wb_ack_o => fmc{n}_mux_wb_in.ack,
wb_stall_o => fmc{n}_mux_wb_in.stall,
wb_irq_o => fmc_host_irq({n}));
cmp_fmc{n}_wb_mux : xwb_crossbar
generic map (
g_num_masters => 2,
g_num_slaves => 1,
g_registered => TRUE,
g_address => c_FMC_MUX_ADDR,
g_mask => c_FMC_MUX_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out({n}),
slave_i(1) => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o(0) => fmc_dp_wb_in({n}),
slave_o(1) => cnx_slave_out(c_WB_SLAVE_FMC{n}),
master_i(0) => fmc{n}_mux_wb_in,
master_o(0) => fmc{n}_mux_wb_out);
fmc{n}_mux_wb_in.err <= '0';
fmc{n}_mux_wb_in.rty <= '0';
-- tristate buffer for the TDC data bus:
fmc{n}_fd_tdc_d_b <= fmc{n}_fd_tdc_data_out when fmc{n}_fd_tdc_data_oe = '1' else (others => 'Z');
fmc{n}_fd_tdc_oe_n_o <= '1';
fmc{n}_fd_tdc_data_in <= fmc{n}_fd_tdc_d_b;
fmc{n}_fd_onewire_b <= '0' when fmc{n}_fd_owr_en = '1' else 'Z';
fmc{n}_fd_owr_in <= fmc{n}_fd_onewire_b;
fmc{n}_fd_scl_in <= fmc{n}_scl_b;
fmc{n}_fd_sda_in <= fmc{n}_sda_b;
software/tools/hdl-gen/builder/fmc-tdc-1ns-5cha/repo.txt deleted 100644 → 0
View file @ a06f02c1
git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git
software/tools/hdl-gen/builder/fmc-tdc-1ns-5cha/svec-fmc0.ucf deleted 100644 → 0
View file @ a06f02c1
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "fmc0_tdc_acam_refclk_p_i" LOC = "H15";
NET "fmc0_tdc_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_acam_refclk_n_i" LOC = "G15";
NET "fmc0_tdc_acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_125m_clk_p_i" LOC = "E16";
NET "fmc0_tdc_125m_clk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_125m_clk_n_i" LOC = "D16";
NET "fmc0_tdc_125m_clk_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_led_trig1_o" LOC = "H13";
NET "fmc0_tdc_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig2_o" LOC = "H11";
NET "fmc0_tdc_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig3_o" LOC = "G11";
NET "fmc0_tdc_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_1_o" LOC = "C16";
NET "fmc0_tdc_term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_2_o" LOC = "A16";
NET "fmc0_tdc_term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef1_i" LOC = "F19";
NET "fmc0_tdc_ef1_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef2_i" LOC = "E19";
NET "fmc0_tdc_ef2_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_3_o" LOC = "F15";
NET "fmc0_tdc_term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_4_o" LOC = "E15";
NET "fmc0_tdc_term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_5_o" LOC = "F13";
NET "fmc0_tdc_term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_status_o" LOC = "E13";
NET "fmc0_tdc_led_status_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig4_o" LOC = "L11";
NET "fmc0_tdc_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig5_o" LOC = "K11";
NET "fmc0_tdc_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sclk_o" LOC = "M15";
NET "fmc0_tdc_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_dac_sync_n_o" LOC = "K15";
NET "fmc0_tdc_pll_dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_cs_n_o" LOC = "L14";
NET "fmc0_tdc_pll_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_cs_n_o" LOC = "K14";
NET "fmc0_tdc_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_err_flag_i" LOC = "H16";
NET "fmc0_tdc_err_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_int_flag_i" LOC = "G16";
NET "fmc0_tdc_int_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_dis_o" LOC = "F11";
NET "fmc0_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_stop_dis_o" LOC = "E11";
NET "fmc0_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdo_i" LOC = "L13";
NET "fmc0_tdc_pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_status_i" LOC = "E9";
NET "fmc0_tdc_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdi_o" LOC = "M13";
NET "fmc0_tdc_pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" LOC = "F9";
NET "fmc0_tdc_start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" SLEW = SLOW;
NET "fmc0_tdc_start_from_fpga_o" DRIVE = 4;
NET "fmc0_tdc_data_bus_io[27]" LOC = "E17";
NET "fmc0_tdc_data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[26]" LOC = "F17";
NET "fmc0_tdc_data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[25]" LOC = "F18";
NET "fmc0_tdc_data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[24]" LOC = "G18";
NET "fmc0_tdc_data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[23]" LOC = "F20";
NET "fmc0_tdc_data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[22]" LOC = "G20";
NET "fmc0_tdc_data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[21]" LOC = "E21";
NET "fmc0_tdc_data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[20]" LOC = "F21";
NET "fmc0_tdc_data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[19]" LOC = "K21";
NET "fmc0_tdc_data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[18]" LOC = "L21";
NET "fmc0_tdc_data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[17]" LOC = "L20";
NET "fmc0_tdc_data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[16]" LOC = "M20";
NET "fmc0_tdc_data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[15]" LOC = "F22";
NET "fmc0_tdc_data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[14]" LOC = "G22";
NET "fmc0_tdc_data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[13]" LOC = "L19";
NET "fmc0_tdc_data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[12]" LOC = "M19";
NET "fmc0_tdc_data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[11]" LOC = "E23";
NET "fmc0_tdc_data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[10]" LOC = "F23";
NET "fmc0_tdc_data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[9]" LOC = "A25";
NET "fmc0_tdc_data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[8]" LOC = "B25";
NET "fmc0_tdc_data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[7]" LOC = "G21";
NET "fmc0_tdc_data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[6]" LOC = "C24";
NET "fmc0_tdc_data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[5]" LOC = "H21";
NET "fmc0_tdc_data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[4]" LOC = "D24";
NET "fmc0_tdc_data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[3]" LOC = "D25";
NET "fmc0_tdc_data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[2]" LOC = "E25";
NET "fmc0_tdc_data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[1]" LOC = "H22";
NET "fmc0_tdc_data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[0]" LOC = "J22";
NET "fmc0_tdc_data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[3]" LOC = "F14";
NET "fmc0_tdc_address_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[2]" LOC = "G14";
NET "fmc0_tdc_address_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[1]" LOC = "H14";
NET "fmc0_tdc_address_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[0]" LOC = "J14";
NET "fmc0_tdc_address_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" LOC = "G12";
NET "fmc0_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" SLEW = SLOW;
NET "fmc0_tdc_oe_n_o" DRIVE = 4;
NET "fmc0_tdc_rd_n_o" LOC = "A15";
NET "fmc0_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_rd_n_o" SLEW = SLOW;
NET "fmc0_tdc_rd_n_o" DRIVE = 4;
NET "fmc0_tdc_wr_n_o" LOC = "B15";
NET "fmc0_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_wr_n_o" SLEW = SLOW;
NET "fmc0_tdc_wr_n_o" DRIVE = 4;
NET "fmc0_tdc_enable_inputs_o" LOC = "J12";
NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_onewire_b" LOC = "H12";
NET "fmc0_tdc_onewire_b" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# input clocks
NET "fmc0_tdc_125m_clk_n_i" TNM_NET = fmc0_tdc_125m_clk_n_i;
TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%;
NET "fmc0_clk_125m" TNM_NET = fmc0_clk_125m;
TIMEGRP "fmc0_sync"="synchronizers" EXCEPT "fmc0_clk_125m";
TIMESPEC TS_fmc0_sync_ffs = FROM fmc0_clk_125m TO "fmc0_sync" 20ns DATAPATHONLY;
software/tools/hdl-gen/builder/fmc-tdc-1ns-5cha/svec-fmc1.ucf deleted 100644 → 0
View file @ a06f02c1
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 1
NET "fmc1_tdc_acam_refclk_p_i" LOC = AF16;
NET "fmc1_tdc_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_acam_refclk_n_i" LOC = AG16;
NET "fmc1_tdc_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_125m_clk_p_i" LOC = AH16;
NET "fmc1_tdc_125m_clk_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_125m_clk_n_i" LOC = AK16;
NET "fmc1_tdc_125m_clk_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_led_trig1_o" LOC = Y20;
NET "fmc1_tdc_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig2_o" LOC = W19;
NET "fmc1_tdc_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig3_o" LOC = Y19;
NET "fmc1_tdc_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_1_o" LOC = AJ17;
NET "fmc1_tdc_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_2_o" LOC = AK17;
NET "fmc1_tdc_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef1_i" LOC = AB14;
NET "fmc1_tdc_ef1_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef2_i" LOC = AC14;
NET "fmc1_tdc_ef2_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_3_o" LOC = AE19;
NET "fmc1_tdc_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_4_o" LOC = AF19;
NET "fmc1_tdc_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_5_o" LOC = AE24;
NET "fmc1_tdc_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_status_o" LOC = AF24;
NET "fmc1_tdc_led_status_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig4_o" LOC = Y21;
NET "fmc1_tdc_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig5_o" LOC = AA21;
NET "fmc1_tdc_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sclk_o" LOC = AF25;
NET "fmc1_tdc_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_dac_sync_n_o" LOC = AG25;
NET "fmc1_tdc_pll_dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_cs_n_o" LOC = AC19;
NET "fmc1_tdc_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_cs_n_o" LOC = AD19;
NET "fmc1_tdc_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_err_flag_i" LOC = Y17;
NET "fmc1_tdc_err_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_int_flag_i" LOC = AA17;
NET "fmc1_tdc_int_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_dis_o" LOC = AB17;
NET "fmc1_tdc_start_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_stop_dis_o" LOC = AD17;
NET "fmc1_tdc_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdo_i" LOC = AC20;
NET "fmc1_tdc_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_status_i" LOC = AD24;
NET "fmc1_tdc_pll_status_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdi_o" LOC = AB20;
NET "fmc1_tdc_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_from_fpga_o" LOC = AC24;
NET "fmc1_tdc_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[27]" LOC = AA15;
NET "fmc1_tdc_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[26]" LOC = Y15;
NET "fmc1_tdc_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[25]" LOC = AD15;
NET "fmc1_tdc_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[24]" LOC = AC15;
NET "fmc1_tdc_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[23]" LOC = AB16;
NET "fmc1_tdc_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[22]" LOC = Y16;
NET "fmc1_tdc_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[21]" LOC = AF15;
NET "fmc1_tdc_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[20]" LOC = AE15;
NET "fmc1_tdc_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[19]" LOC = AA14;
NET "fmc1_tdc_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[18]" LOC = Y14;
NET "fmc1_tdc_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[17]" LOC = Y13;
NET "fmc1_tdc_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[16]" LOC = W14;
NET "fmc1_tdc_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[15]" LOC = AE12;
NET "fmc1_tdc_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[14]" LOC = AD12;
NET "fmc1_tdc_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[13]" LOC = AF11;
NET "fmc1_tdc_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[12]" LOC = AE11;
NET "fmc1_tdc_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[11]" LOC = AC12;
NET "fmc1_tdc_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[10]" LOC = AB12;
NET "fmc1_tdc_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[9]" LOC = AE10;
NET "fmc1_tdc_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[8]" LOC = AD10;
NET "fmc1_tdc_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[7]" LOC = AH8;
NET "fmc1_tdc_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[6]" LOC = AK15;
NET "fmc1_tdc_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[5]" LOC = AG8;
NET "fmc1_tdc_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[4]" LOC = AJ15;
NET "fmc1_tdc_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[3]" LOC = AF13;
NET "fmc1_tdc_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[2]" LOC = AE13;
NET "fmc1_tdc_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[1]" LOC = AD11;
NET "fmc1_tdc_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[0]" LOC = AC11;
NET "fmc1_tdc_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[3]" LOC = AF23;
NET "fmc1_tdc_address_o[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[2]" LOC = AE23;
NET "fmc1_tdc_address_o[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[1]" LOC = AF21;
NET "fmc1_tdc_address_o[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[0]" LOC = AE21;
NET "fmc1_tdc_address_o[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_oe_n_o" LOC = AD22;
NET "fmc1_tdc_oe_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_rd_n_o" LOC = AD16;
NET "fmc1_tdc_rd_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_wr_n_o" LOC = AC16;
NET "fmc1_tdc_wr_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_enable_inputs_o" LOC = AA19;
NET "fmc1_tdc_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_onewire_b" LOC = AB19;
NET "fmc1_tdc_onewire_b" IOSTANDARD = LVCMOS25;
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
# input clocks
NET "fmc1_tdc_125m_clk_n_i" TNM_NET = fmc1_tdc_125m_clk_n_i;
TIMESPEC TS_fmc1_tdc_125m_clk_n_i = PERIOD "fmc1_tdc_125m_clk_n_i" 8 ns HIGH 50%;
NET "fmc1_clk_125m" TNM_NET = fmc1_clk_125m;
TIMEGRP "fmc1_sync"="synchronizers" EXCEPT "fmc1_clk_125m";
TIMESPEC TS_fmc1_sync_ffs = FROM fmc1_clk_125m TO "fmc1_sync" 20ns DATAPATHONLY;
software/tools/hdl-gen/builder/fmc-tdc-1ns-5cha/top.vhd deleted 100644 → 0
View file @ a06f02c1
[use]
use work.tdc_core_pkg.all;
[ports]
---------------------------------------------------------------------------
-- FMC slot {n} pins (TDC mezzanine)
---------------------------------------------------------------------------
-- TDC1 PLL AD9516 and DAC AD5662 interface
fmc{n}_tdc_pll_sclk_o : out std_logic;
fmc{n}_tdc_pll_sdi_o : out std_logic;
fmc{n}_tdc_pll_cs_n_o : out std_logic;
fmc{n}_tdc_pll_dac_sync_n_o : out std_logic;
fmc{n}_tdc_pll_sdo_i : in std_logic;
fmc{n}_tdc_pll_status_i : in std_logic;
fmc{n}_tdc_125m_clk_p_i : in std_logic;
fmc{n}_tdc_125m_clk_n_i : in std_logic;
fmc{n}_tdc_acam_refclk_p_i : in std_logic;
fmc{n}_tdc_acam_refclk_n_i : in std_logic;
-- TDC1 ACAM timing interface
fmc{n}_tdc_start_from_fpga_o : out std_logic;
fmc{n}_tdc_err_flag_i : in std_logic;
fmc{n}_tdc_int_flag_i : in std_logic;
fmc{n}_tdc_start_dis_o : out std_logic;
fmc{n}_tdc_stop_dis_o : out std_logic;
-- TDC1 ACAM data interface
fmc{n}_tdc_data_bus_io : inout std_logic_vector(27 downto 0);
fmc{n}_tdc_address_o : out std_logic_vector(3 downto 0);
fmc{n}_tdc_cs_n_o : out std_logic;
fmc{n}_tdc_oe_n_o : out std_logic;
fmc{n}_tdc_rd_n_o : out std_logic;
fmc{n}_tdc_wr_n_o : out std_logic;
fmc{n}_tdc_ef1_i : in std_logic;
fmc{n}_tdc_ef2_i : in std_logic;
-- TDC1 Input Logic
fmc{n}_tdc_enable_inputs_o : out std_logic;
fmc{n}_tdc_term_en_1_o : out std_logic;
fmc{n}_tdc_term_en_2_o : out std_logic;
fmc{n}_tdc_term_en_3_o : out std_logic;
fmc{n}_tdc_term_en_4_o : out std_logic;
fmc{n}_tdc_term_en_5_o : out std_logic;
-- TDC1 1-wire UniqueID & Thermometer
fmc{n}_tdc_onewire_b : inout std_logic;
-- TDC1 EEPROM I2C
fmc{n}_tdc_scl_b : inout std_logic;
fmc{n}_tdc_sda_b : inout std_logic;
-- TDC1 LEDs
fmc{n}_tdc_led_status_o : out std_logic;
fmc{n}_tdc_led_trig1_o : out std_logic;
fmc{n}_tdc_led_trig2_o : out std_logic;
fmc{n}_tdc_led_trig3_o : out std_logic;
fmc{n}_tdc_led_trig4_o : out std_logic;
fmc{n}_tdc_led_trig5_o : out std_logic;
-- TDC1 Input channels
-- also arriving to the FPGA (not used for the moment)
fmc{n}_tdc_in_fpga_1_i : in std_logic;
fmc{n}_tdc_in_fpga_2_i : in std_logic;
fmc{n}_tdc_in_fpga_3_i : in std_logic;
fmc{n}_tdc_in_fpga_4_i : in std_logic;
fmc{n}_tdc_in_fpga_5_i : in std_logic;
[sdb-decl]
constant c_tdc{n}_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"00007FFF", x"00000000");
[sdb-layout]
c_WB_SLAVE_FMC{n} => f_sdb_embed_bridge(c_tdc{n}_bridge_sdb, x"{addr}"),
[body]
-----------------------------------------------------------------------------
-- FMC TDC (SVEC slot #{n})
-----------------------------------------------------------------------------
U_TDC_Core : fmc_tdc_wrapper
generic map (
g_simulation => f_int2bool(g_simulation),
g_with_direct_readout => TRUE)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
pll_sclk_o => fmc{n}_tdc_pll_sclk_o,
pll_sdi_o => fmc{n}_tdc_pll_sdi_o,
pll_cs_o => fmc{n}_tdc_pll_cs_n_o,
pll_dac_sync_o => fmc{n}_tdc_pll_dac_sync_n_o,
pll_sdo_i => fmc{n}_tdc_pll_sdo_i,
pll_status_i => fmc{n}_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc{n}_tdc_125m_clk_p_i,
tdc_clk_125m_n_i => fmc{n}_tdc_125m_clk_n_i,
acam_refclk_p_i => fmc{n}_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc{n}_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc{n}_tdc_start_from_fpga_o,
err_flag_i => fmc{n}_tdc_err_flag_i,
int_flag_i => fmc{n}_tdc_int_flag_i,
start_dis_o => fmc{n}_tdc_start_dis_o,
stop_dis_o => fmc{n}_tdc_stop_dis_o,
data_bus_io => fmc{n}_tdc_data_bus_io,
address_o => fmc{n}_tdc_address_o,
cs_n_o => fmc{n}_tdc_cs_n_o,
oe_n_o => fmc{n}_tdc_oe_n_o,
rd_n_o => fmc{n}_tdc_rd_n_o,
wr_n_o => fmc{n}_tdc_wr_n_o,
ef1_i => fmc{n}_tdc_ef1_i,
ef2_i => fmc{n}_tdc_ef2_i,
enable_inputs_o => fmc{n}_tdc_enable_inputs_o,
term_en_1_o => fmc{n}_tdc_term_en_1_o,
term_en_2_o => fmc{n}_tdc_term_en_2_o,
term_en_3_o => fmc{n}_tdc_term_en_3_o,
term_en_4_o => fmc{n}_tdc_term_en_4_o,
term_en_5_o => fmc{n}_tdc_term_en_5_o,
tdc_led_status_o => fmc{n}_tdc_led_status_o,
tdc_led_trig1_o => fmc{n}_tdc_led_trig1_o,
tdc_led_trig2_o => fmc{n}_tdc_led_trig2_o,
tdc_led_trig3_o => fmc{n}_tdc_led_trig3_o,
tdc_led_trig4_o => fmc{n}_tdc_led_trig4_o,
tdc_led_trig5_o => fmc{n}_tdc_led_trig5_o,
tdc_in_fpga_1_i => fmc{n}_tdc_in_fpga_1_i,
tdc_in_fpga_2_i => fmc{n}_tdc_in_fpga_2_i,
tdc_in_fpga_3_i => fmc{n}_tdc_in_fpga_3_i,
tdc_in_fpga_4_i => fmc{n}_tdc_in_fpga_4_i,
tdc_in_fpga_5_i => fmc{n}_tdc_in_fpga_5_i,
mezz_scl_i => fmc{n}_scl_b,
mezz_sda_i => fmc{n}_sda_b,
mezz_scl_o => fmc{n}_scl_out,
mezz_sda_o => fmc{n}_sda_out,
mezz_one_wire_b => fmc{n}_tdc_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en({n}),
tm_clk_aux_locked_i => tm_clk_aux_locked({n}),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr({n}),
direct_slave_i => fmc_dp_wb_out({n}),
direct_slave_o => fmc_dp_wb_in({n}),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC{n}),
irq_o => fmc_host_irq({n}),
clk_125m_tdc_o => fmc{n}_clk_125m);
software/tools/hdl-gen/builder/spec-lib/carrier_csr.vhd deleted 100644 → 0
View file @ a06f02c1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.carrier_csr_wbgen2_pkg.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_carrier_csr_in_registers;
regs_o : out t_carrier_csr_out_registers
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_rst_fmc0_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= regs_i.carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= regs_i.carrier_reserved_i;
rddata_reg(31 downto 16) <= regs_i.carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.stat_fmc_pres_i;
rddata_reg(1) <= regs_i.stat_p2l_pll_lck_i;
rddata_reg(2) <= regs_i.stat_sys_pll_lck_i;
rddata_reg(3) <= regs_i.stat_ddr3_cal_done_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Green LED
regs_o.ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED
regs_o.ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
regs_o.ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- State of the reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
software/tools/hdl-gen/builder/spec-lib/carrier_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ a06f02c1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package carrier_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_carrier_csr_in_registers is record
carrier_pcb_rev_i : std_logic_vector(3 downto 0);
carrier_reserved_i : std_logic_vector(11 downto 0);
carrier_type_i : std_logic_vector(15 downto 0);
stat_fmc_pres_i : std_logic;
stat_p2l_pll_lck_i : std_logic;
stat_sys_pll_lck_i : std_logic;
stat_ddr3_cal_done_i : std_logic;
end record;
constant c_carrier_csr_in_registers_init_value: t_carrier_csr_in_registers := (
carrier_pcb_rev_i => (others => '0'),
carrier_reserved_i => (others => '0'),
carrier_type_i => (others => '0'),
stat_fmc_pres_i => '0',
stat_p2l_pll_lck_i => '0',
stat_sys_pll_lck_i => '0',
stat_ddr3_cal_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_carrier_csr_out_registers is record
ctrl_led_green_o : std_logic;
ctrl_led_red_o : std_logic;
ctrl_dac_clr_n_o : std_logic;
rst_fmc0_o : std_logic;
end record;
constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
ctrl_led_green_o => '0',
ctrl_led_red_o => '0',
ctrl_dac_clr_n_o => '0',
rst_fmc0_o => '0'
);
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body carrier_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers is
variable tmp: t_carrier_csr_in_registers;
begin
tmp.carrier_pcb_rev_i := f_x_to_zero(left.carrier_pcb_rev_i) or f_x_to_zero(right.carrier_pcb_rev_i);
tmp.carrier_reserved_i := f_x_to_zero(left.carrier_reserved_i) or f_x_to_zero(right.carrier_reserved_i);
tmp.carrier_type_i := f_x_to_zero(left.carrier_type_i) or f_x_to_zero(right.carrier_type_i);
tmp.stat_fmc_pres_i := f_x_to_zero(left.stat_fmc_pres_i) or f_x_to_zero(right.stat_fmc_pres_i);
tmp.stat_p2l_pll_lck_i := f_x_to_zero(left.stat_p2l_pll_lck_i) or f_x_to_zero(right.stat_p2l_pll_lck_i);
tmp.stat_sys_pll_lck_i := f_x_to_zero(left.stat_sys_pll_lck_i) or f_x_to_zero(right.stat_sys_pll_lck_i);
tmp.stat_ddr3_cal_done_i := f_x_to_zero(left.stat_ddr3_cal_done_i) or f_x_to_zero(right.stat_ddr3_cal_done_i);
return tmp;
end function;
end package body;
software/tools/hdl-gen/builder/spec-lib/dma_eic.vhd deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/builder/spec-lib/wb_gen/Makefile deleted 100644 → 0
View file @ a06f02c1
WBGEN2=$(shell which wbgen2)
RTL=../
TEX=../../../../doc/manual/spec/
all: carrier_csr dma_eic
carrier_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
dma_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
software/tools/hdl-gen/builder/spec-lib/wb_gen/carrier_csr.h deleted 100644 → 0
View file @ a06f02c1
/*
Register definitions for slave core: Carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Mon Feb 26 15:24:45 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 4)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 4
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Status */
/* definitions for field: FMC presence in reg: Status */
#define CARRIER_CSR_STAT_FMC_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: GN4142 core P2L PLL status in reg: Status */
#define CARRIER_CSR_STAT_P2L_PLL_LCK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: DDR3 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR3_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Control */
/* definitions for field: Green LED in reg: Control */
#define CARRIER_CSR_CTRL_LED_GREEN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Red LED in reg: Control */
#define CARRIER_CSR_CTRL_LED_RED WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0 WBGEN2_GEN_MASK(0, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x8]: REG Control */
uint32_t CTRL;
/* [0xc]: REG Reset Register */
uint32_t RST;
};
#endif
software/tools/hdl-gen/builder/spec-lib/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ a06f02c1
peripheral {
name = "Carrier control and status registers";
description = "Wishbone slave for control and status registers related to the FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 12;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC presence";
description = "0: FMC slot is populated\n1: FMC slot is not populated.";
prefix = "fmc_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "GN4142 core P2L PLL status";
description = "0: not locked\n1: locked.";
prefix = "p2l_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr3_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Green LED";
description = "Manual control of the front panel green LED (unused in the fmc-adc application)";
prefix = "led_green";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Red LED";
description = "Manual control of the front panel red LED (unused in the fmc-adc application)";
prefix = "led_red";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC clear";
description = "Active low clear signal for VCXO DACs";
prefix = "dac_clr_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanine including the ddr interface and the time-tagging core.";
field {
name = "State of the reset line";
description = "write 0: Normal FMC operation\
write 1: FMC is held in reset";
type = BIT;
size = 1;
prefix = "fmc0";
access_bus = WRITE;
access_dev = READ;
};
};
};
software/tools/hdl-gen/builder/spec-lib/wb_gen/dma_eic.h deleted 100644 → 0
View file @ a06f02c1
/*
Register definitions for slave core: GN4124 DMA enhanced interrupt controller
* File : dma_eic.h
* Author : auto-generated by wbgen2 from dma_eic.wb
* Created : Thu Jun 16 16:45:19 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_DMA_EIC_WB
#define __WBGEN2_REGDEFS_DMA_EIC_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: DMA done interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: DMA done interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: DMA done interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: DMA done interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
PACKED struct DMA_EIC_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
software/tools/hdl-gen/builder/spec-lib/wb_gen/dma_eic.wb deleted 100644 → 0
View file @ a06f02c1
peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
software/tools/hdl-gen/builder/spec/Manifest-syn.py deleted 100644 → 0
View file @ a06f02c1
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "spec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "{name}_top"
syn_project = "{name}.xise"
syn_tool = "ise"
fetchto = "{fetchto}"
ctrls = ["bank3_64b_32b"]
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files = [
"{name}.ucf",
]
modules = {{
"local" : [
"../../top/{name}",
],
}}
software/tools/hdl-gen/builder/spec/Manifest-top.py deleted 100644 → 0
View file @ a06f02c1
files = [
"{name}_top.vhd",
"../../../spec-lib/carrier_csr_wbgen2_pkg.vhd",
"../../../spec-lib/carrier_csr.vhd",
"../../../spec-lib/dma_eic.vhd",
]
fetchto = "{fetchto}"
modules = {{
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
{modules}
],
}}
software/tools/hdl-gen/builder/spec/syn_extra_steps.tcl deleted 100644 → 0
View file @ a06f02c1
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project save
xilinx::project close
software/tools/hdl-gen/builder/spec/top.ucf deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/builder/spec/top.vhd deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/builder/svec/Manifest-syn.py deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/builder/svec/Manifest-top.py deleted 100644 → 0
View file @ a06f02c1
files = [
"{name}_top.vhd",
]
fetchto = "{fetchto}"
modules = {{
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
{modules}
],
}}
software/tools/hdl-gen/builder/svec/top.ucf deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/builder/svec/top.vhd deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/builder/wrtd_builder.py deleted 100755 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/configs/adc.yaml deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/configs/fd_tdc.yaml deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/configs/spec_adc.yaml deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/configs/tdc.yaml deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
software/tools/hdl-gen/configs/tdc_fd.yaml deleted 100644 → 0
View file @ a06f02c1
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment