[hdl] make SPEC testbench finish automatically when done

fc0b5603 · Dimitris Lampridis · 86d87a5a · fc0b5603
Commit fc0b5603 authored Aug 08, 2019 by Dimitris Lampridis
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Showing with 4 additions and 1 deletion

main.sv hdl/testbench/wrtd_ref_spec150t_adc/main.sv +4 -1

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--- a/hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/main.sv
@@ -54,6 +54,8 @@ module main;

   const uint64_t MT_BASE = 'h0002_0000;

+   int sim_end = 0;
+
   initial begin

      uint64_t val, expected;
@@ -222,6 +224,7 @@ module main;

      join

+      sim_end = 1;

   end

@@ -241,7 +244,7 @@ module main;
      $display("-------------------");
      $display();

-      #5000us;
+      wait (sim_end == 1);

      $display();
      $display("Simulation PASSED");