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White Rabbit Trigger Distribution
Commit e6e1f0b2 authored by Tristan Gingold's avatar Tristan Gingold
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list_tdc_fd: add mock turtle.

parent 9652761d
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Showing with 75 additions and 18 deletions
.gitmodules
View file @ e6e1f0b2
......@@ -19,3 +19,6 @@
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "hdl/ip_cores/urv-core"]
path = hdl/ip_cores/urv-core
url = git://ohwr.org/hdl-core-lib/urv-core.git
mock-turtle @ 06eec248
Subproject commit 52e7ff854766b4dae1de7e1ea63d7f0c3d197d44
Subproject commit 06eec24886b926745aa8c85cf6ce27334b3a7df3
urv-core @ 890dfda6
Subproject commit 890dfda6d8a9de5a1cf7e3aa49304d3778745cb0
hdl/top/svec/list_tdc_fd/Manifest.py
View file @ e6e1f0b2
......@@ -3,7 +3,8 @@ files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf" ]
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../../ip_cores/mock-turtle",
"local" : [ "../../../ip_cores/mock-turtle/hdl/rtl",
"../../../ip_cores/urv-core",
"../../../ip_cores/general-cores",
"../../../ip_cores/wr-cores",
"../node_template",
......
hdl/top/svec/list_tdc_fd/svec_top.vhd
View file @ e6e1f0b2
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2018-07-03
-- Last update: 2018-07-04
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -276,7 +276,7 @@ architecture rtl of svec_top is
constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
(0 => x"10000000");
constant c_node_config : t_mt_config :=
constant c_mt_config : t_mt_config :=
(
app_id => x"115790de",
cpu_count => 2,
......@@ -291,13 +291,15 @@ architecture rtl of svec_top is
entries_bits => 3,
width_bits => 7,
header_bits => 2,
endpoint_id => x"0000_0000"),
endpoint_id => x"0000_0000",
enable_config_space => false),
1 => (
-- Log
entries_bits => 7,
width_bits => 4,
header_bits => 2,
endpoint_id => x"0000_0000"),
endpoint_id => x"0000_0000",
enable_config_space => false),
others => c_DUMMY_MT_MQUEUE_SLOT)),
rmq_config => (
slot_count => 1,
......@@ -306,7 +308,8 @@ architecture rtl of svec_top is
entries_bits => 4,
width_bits => 7,
header_bits => 4,
endpoint_id => x"0000_0000"),
endpoint_id => x"0000_0000",
enable_config_space => true),
others => c_DUMMY_MT_MQUEUE_SLOT))),
others => (
0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)),
......@@ -393,7 +396,7 @@ begin
g_with_wr_phy => true,
g_double_wrnode_core_clock => false,
g_with_white_rabbit => true,
g_wr_node_config => c_node_config)
g_mt_config => c_mt_config)
port map (
rst_n_a_i => rst_n_a_i,
rst_n_sys_o => rst_n,
......
hdl/top/svec/node_template/svec_node_template.vhd
View file @ e6e1f0b2
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2018-07-03
-- Last update: 2018-07-04
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -85,7 +85,7 @@ entity svec_node_template is
g_double_wrnode_core_clock : boolean := false;
-- Configuration of the WR Node Core. Fill in according to your needs.
g_wr_node_config : t_mt_config;
g_mt_config : t_mt_config;
-- Use external LEDs. When true, the front panel LEDs on the SVEC are
-- driven by the "led_state_i" signal. Otherwise, they display the default
......@@ -321,7 +321,7 @@ architecture rtl of svec_node_template is
constant c_SLAVE_FMC0 : integer := 0;
constant c_SLAVE_FMC1 : integer := 1;
constant c_SLAVE_WR_CORE : integer := 3;
constant c_SLAVE_WR_NODE : integer := 4;
constant c_SLAVE_MT : integer := 4;
constant c_SLAVE_VIC : integer := 2;
constant c_DESC_SYNTHESIS : integer := 5;
constant c_DESC_REPO_URL : integer := 6;
......@@ -333,7 +333,7 @@ architecture rtl of svec_node_template is
c_SLAVE_FMC1 => g_fmc1_sdb,
c_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00002000"),
c_SLAVE_WR_CORE => f_pick_wr_core_sdb,
c_SLAVE_WR_NODE => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000")
c_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000")
-- c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_sdb_synthesis_info),
-- c_DESC_REPO_URL => f_sdb_embed_repo_url(c_sdb_repo_url)
);
......@@ -385,12 +385,15 @@ architecture rtl of svec_node_template is
signal local_reset_n : std_logic;
signal wrn_irq : std_logic;
signal mt_hmq_in_irq : std_logic;
signal mt_hmq_out_irq : std_logic;
signal mt_console_irq : std_logic;
signal mt_notify_irq : std_logic;
signal vic_master_irq : std_logic;
signal pins : std_logic_vector(31 downto 0);
signal pps : std_logic;
signal vic_master_irq : std_logic;
function f_bool2int (x : boolean) return integer is
begin
if(x) then
......@@ -414,6 +417,14 @@ architecture rtl of svec_node_template is
return tmp;
end f_resize_slv;
signal wrc_src_out : t_wrf_source_out;
signal wrc_src_in : t_wrf_source_in;
signal wrc_snk_out : t_wrf_sink_out;
signal wrc_snk_in : t_wrf_sink_in;
signal mt2ep : t_mt_rmq_endpoint_iface_out;
signal ep2mt : t_mt_rmq_endpoint_iface_in;
signal ebm_src_out : t_wrf_source_out;
signal ebm_src_in : t_wrf_source_in;
signal ebs_snk_in : t_wrf_sink_in;
......@@ -443,7 +454,6 @@ architecture rtl of svec_node_template is
signal tm : t_mt_timing_if;
signal wrn_gpio_out, wrn_gpio_in : std_logic_vector(31 downto 0);
signal rst_net_n : std_logic;
signal wrn_debug_msg_irq : std_logic;
begin
......@@ -795,7 +805,7 @@ begin
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 4,
g_num_interrupts => 6,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => clk_sys,
......@@ -804,10 +814,49 @@ begin
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => fmc0_host_irq_i,
irqs_i(1) => fmc1_host_irq_i,
irqs_i(2) => wrn_irq,
irqs_i(3) => wrn_debug_msg_irq,
irqs_i(2) => mt_hmq_in_irq,
irqs_i(3) => mt_hmq_out_irq,
irqs_i(4) => mt_console_irq,
irqs_i(5) => mt_notify_irq,
irq_master_o => vic_master_irq);
U_Mock_Turtle : mock_turtle_core
generic map (
g_CONFIG => g_mt_config,
g_WITH_WHITE_RABBIT => true)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
dp_master_o(0) => fmc0_dp_wb_o,
dp_master_o(1) => fmc1_dp_wb_o,
dp_master_i(0) => fmc0_dp_wb_i,
dp_master_i(1) => fmc1_dp_wb_i,
host_slave_i => cnx_master_out(c_SLAVE_MT),
host_slave_o => cnx_master_in(c_SLAVE_MT),
hmq_in_irq_o => mt_hmq_in_irq,
hmq_out_irq_o => mt_hmq_out_irq,
notify_irq_o => mt_notify_irq,
console_irq_o => mt_console_irq);
U_Ethernet_Endpoint: entity work.mt_rmq_ethernet_endpoint
generic map (
g_CONFIG => g_MT_CONFIG)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
mt_rmq_i => mt2ep,
mt_rmq_o => ep2mt,
eth_src_i => wrc_snk_out,
eth_src_o => wrc_snk_in,
eth_snk_i => wrc_src_out,
eth_snk_o => wrc_src_in
);
gen_wr_node_with_white_rabbit : if g_with_white_rabbit generate
......
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