Commit bc224077 authored by Dimitris Lampridis's avatar Dimitris Lampridis

Update FMC-TDC to use improved direct readout with support for offsets and bug…

Update FMC-TDC to use improved direct readout with support for offsets and bug fix related to fake tstamps from ACAM FIFO2
parent 834c4951
Subproject commit 84ffc99fcd77897a9610b7736a2f95a353d10717
Subproject commit 31e4f6f5afe6446ac362471881bad4a39255f578
......@@ -44,6 +44,7 @@ module simple_tdc_driver
typedef struct {
int channel;
time ts;
time duration;
} acam_fifo_entry;
acam_fifo_entry pulses[$];
......@@ -62,8 +63,8 @@ module simple_tdc_driver
assign data = rdata;
assign intflag = start[7];
task push_pulse(int channel, time ts);
pulses.push_back('{channel: channel, ts: ts});
task push_pulse(int channel, time ts, time duration);
pulses.push_back('{channel: channel, ts: ts, duration: duration});
endtask
// Convert trigger to ACAM data
......@@ -84,7 +85,7 @@ module simple_tdc_driver
const int fifo_n = t.channel / 4;
logic [27:0] val;
#(t.ts - now) ;
#(t.ts - now);
val[27:26] = t.channel & 2'b11;
val[25:18] = start;
......@@ -95,6 +96,15 @@ module simple_tdc_driver
$realtime, t.ts, t.channel, start, val[16:0], start_time);
fifos[t.channel / 4].push_back(val);
#(t.duration);
val[27:26] = t.channel & 2'b11;
val[25:18] = start;
val[17] = 1'b0;
val[16:0] = (t.duration + t.ts - start_time) / 81ps;
fifos[t.channel / 4].push_back(val);
end
end
......@@ -380,18 +390,18 @@ module dut_env
// Initial processes
//---------------------------------------------------------------------------
task push_pulse(int channel, time ts);
TDC.push_pulse(channel, ts);
FDL.push_pulse(channel, ts + 100us); // Delay time (from fd firmware)
task push_pulse(int channel, time ts, time duration, time delay);
TDC.push_pulse(channel, ts, duration);
FDL.push_pulse(channel, ts + delay); // Delay time (from fd firmware)
endtask
initial begin
// No pulse before: WR (300us) + TDC setup.
automatic time start = 850us;
push_pulse(0, start + 10us);
push_pulse(1, start + 30us);
push_pulse(2, start + 50us);
push_pulse(0, start + 10us, 100ns, 100us);
push_pulse(1, start + 30us, 100ns, 100us);
push_pulse(2, start + 50us, 100ns, 100us);
#(start + 1000us) ;
// Should have been finished by the FD monitor.
......
......@@ -73,7 +73,6 @@ module main;
of CBusAccessor_VME64x when performing reads/writes. */
acc.set_default_xfer_size(A32 | D32 | SINGLE);
acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
#5us;
dev = new (acc, `MT_BASE, MtIrqMonitor, "DUT");
......@@ -104,14 +103,8 @@ module main;
dev.set_rule ( "rule5", "LC-I3", "NET2", 0 );
dev.enable_rule ( "rule5" );
// Set dead-time
acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
#5us;
// Enable channels
acc.write(`TDC_DIRECT_BASE + 'h0, 'h1f);
// Force start_fpga from TDC to make sure that the FSM has been started
force DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga = 'b1;
#100ns;
......
......@@ -712,6 +712,9 @@ begin -- architecture arch
U_TDC_Core : entity work.fmc_tdc_wrapper
generic map (
g_SIMULATION => f_int2bool(g_SIMULATION),
g_PULSE_WIDTH_FILTER => FALSE,
g_USE_FIFO_READOUT => FALSE,
g_USE_DMA_READOUT => FALSE,
g_WITH_DIRECT_READOUT => TRUE)
port map (
clk_sys_i => clk_sys_62m5,
......
......@@ -12,20 +12,16 @@
#include "hw/tdc_regs.h"
#include "hw/acam_gpx.h"
#define BASE_DP_TDC_REGS 0x2000
#define BASE_DP_TDC_DIRECT 0x8000
#include "wrtd-tdc.h"
#define TDC_NUM_CHANNELS 5
#define NB_ACAM_REGS 11
#define TDC_VCXO_DEFAULT_TUNE 32000
#define DEFAULT_DEAD_TIME (80000/16)
struct wrtd_tdc_calibration calib = {
.offset_tai = { 0, 0, 0, 0, 0},
.offset_coarse = {-98, -98, -98, -98, -98},
.offset_frac = { 0, 0, 0, 0, 0},
};
struct wrtd_tdc_dev {
uint32_t io_addr;
/* FIXME: base channel (to create the event id). */
};
static inline void tdc_writel(const struct wrtd_tdc_dev *dev,
......@@ -173,20 +169,28 @@ static void tdc_enable_acquisition(struct wrtd_tdc_dev *tdc, int enable)
}
}
/* FIXME missing all calibration */
static inline void tdc_apply_calibration(struct wrtd_tdc_dev *tdc, int index)
{
uint32_t chan_addr = BASE_DP_TDC_CH1 + (index * 0x100);
tdc_writel(tdc, calib.offset_tai[index], chan_addr + 0x0C);
tdc_writel(tdc, calib.offset_coarse[index], chan_addr + 0x10);
tdc_writel(tdc, calib.offset_frac[index], chan_addr + 0x14);
}
static int tdc_init(struct wrtd_tdc_dev *tdc)
{
int err;
int err, i;
pr_debug("%s: Initializing the TDC...\n\r", __func__);
/* Initialize the TDC FIFO (channels disabled, default dead time) */
/* Initialize the direct readout interface (channels disabled, default dead time) */
tdc_writel(tdc, 0x0, BASE_DP_TDC_DIRECT + DR_REG_CHAN_ENABLE);
tdc_writel(tdc, DEFAULT_DEAD_TIME, BASE_DP_TDC_DIRECT + DR_REG_DEAD_TIME);
#ifndef SIMULATION
tdc_enable_acquisition(tdc, 0);
#ifndef SIMULATION
err = tdc_acam_init(tdc);
if (err)
return err;
......@@ -199,9 +203,17 @@ static int tdc_init(struct wrtd_tdc_dev *tdc)
if (err)
return err;
tdc_enable_acquisition(tdc, 1);
#endif
tdc_enable_acquisition(tdc, 1);
for (i = 0; i < TDC_NUM_CHANNELS; i++) {
tdc_apply_calibration(tdc, i);
}
/* Enable all direct readout channels */
tdc_writel(tdc, 0x1f, BASE_DP_TDC_DIRECT + DR_REG_CHAN_ENABLE);
pr_debug("%s: TDC initialization complete\n\r", __func__);
return 0;
......
/**
* @file wrtd-tdc.h
*
* Copyright (c) 2018-2019 CERN (home.cern)
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
#ifndef __WRTD_TDC_H
#define __WRTD_TDC_H
#include "wrtd-common.h"
#define BASE_DP_TDC_REGS 0x2000
#define BASE_DP_TDC_CH1 0x5000
#define BASE_DP_TDC_DIRECT 0x8000
#define TDC_NUM_CHANNELS 5
#define NB_ACAM_REGS 11
#define TDC_VCXO_DEFAULT_TUNE 32000
/* Dead time per TDC channel, in 8ns ticks.
The core adds one more tick to this value */
#define DEFAULT_DEAD_TIME 0xC
struct wrtd_tdc_calibration {
int32_t offset_tai[TDC_NUM_CHANNELS];
int32_t offset_coarse[TDC_NUM_CHANNELS];
int32_t offset_frac[TDC_NUM_CHANNELS];
};
#endif
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