Commit b8943d1f authored by Dimitris Lampridis's avatar Dimitris Lampridis

[hdl] updated fdelay core with improved timing

parent 4d3a7c74
......@@ -239,15 +239,17 @@ static void fd_output (struct wrtd_fd_dev *fd, unsigned channel)
return;
}
/* Apply zero offset calibration value */
if (calib.zero_offset_ps[channel] >= 0)
/* Apply zero offset calibration value if necessary */
if (calib.zero_offset_ps[channel] == 0)
ts = ev->ts;
else if (calib.zero_offset_ps[channel] > 0)
ts_add3_ps(&ts, &ev->ts, calib.zero_offset_ps[channel]);
else
ts_sub3_ps(&ts, &ev->ts, -calib.zero_offset_ps[channel]);
/* Program the output start time */
fd_ch_writel(out, ts.seconds, FD_REG_U_STARTL);
fd_ch_writel(out, ts.ns / 8, FD_REG_C_START);
fd_ch_writel(out, ts.ns >> 3, FD_REG_C_START);
fd_ch_writel(out, ((ts.ns & 7) << 9) | (ts.frac >> (32 - 9)),
FD_REG_F_START);
......@@ -255,7 +257,7 @@ static void fd_output (struct wrtd_fd_dev *fd, unsigned channel)
ts_add2_ns(&ts, out->width_ns);
fd_ch_writel(out, ts.seconds, FD_REG_U_ENDL);
fd_ch_writel(out, ts.ns / 8, FD_REG_C_END);
fd_ch_writel(out, ts.ns >> 3, FD_REG_C_END);
fd_ch_writel(out, ((ts.ns & 7) << 9) | (ts.frac >> (32 - 9)),
FD_REG_F_END);
fd_ch_writel(out, 0, FD_REG_RCR);
......@@ -312,7 +314,7 @@ static void wrtd_fd_data_init(struct wrtd_fd_dev *fd)
fd->channels[i].channel_addr = fd->io_addr + 0x100 + i * 0x100;
pulse_queue_init(&fd->channels[i].queue);
fd->channels[i].idle = 1;
fd->channels[i].width_ns = 10000; // 10us
fd->channels[i].width_ns = 100; // 100ns
fd->channels[i].last_programmed_sec = 0;
fd->channels[i].last_programmed_ns = 0;
}
......
......@@ -15,9 +15,9 @@
#include "wrtd-tdc.h"
struct wrtd_tdc_calibration calib = {
.offset_tai = { 0, 0, 0, 0, 0},
.offset_coarse = {-98, -98, -98, -98, -98},
.offset_frac = { 0, 0, 0, 0, 0},
.offset_tai = { 0, 0, 0, 0, 0},
.offset_coarse = { -94, -94, -94, -94, -94},
.offset_frac = { 200, 200, 400, 400, 400},
};
struct wrtd_tdc_dev {
......@@ -43,9 +43,7 @@ static const struct {
0, AR0_ROsc | AR0_HQSel | AR0_TRiseEn(0) |
AR0_TRiseEn(1) | AR0_TRiseEn(2) |
AR0_TRiseEn(3) | AR0_TRiseEn(4) |
AR0_TRiseEn(5) |
AR0_TFallEn(1) | AR0_TFallEn(2) |
AR0_TFallEn(3) | AR0_TFallEn(4) | AR0_TFallEn(5)}, {
AR0_TRiseEn(5)}, {
1, 0}, {
2, AR2_IMode | AR2_Disable(6) | AR2_Disable(7) | AR2_Disable(8)}, {
3, 0}, {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment