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White Rabbit Trigger Distribution
Commit b403b9ec authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: further fine-tuning of timing constraints

parent b94b6b8c
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Showing with 14 additions and 3 deletions
general-cores @ 7faa55fe
Subproject commit 01731cd1675402d6b2a8139ec7c8ad9bf64a3507
Subproject commit 7faa55fe373b380665dac981b572867d74a8ed6a
wr-cores @ 9a218b52
Subproject commit 02873972e7d9984933ad024e98fe32b88787704e
Subproject commit 9a218b5250ba26d9e04382f54c93a06885a0a655
hdl/syn/svec/list_tdc_fd/svec_list_top.ucf
View file @ b403b9ec
......@@ -719,11 +719,22 @@ TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "synchronizers" 8ns DATAPATH
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "synchronizers" 8ns DATAPATHONLY;
# one more path where TAI time crosses from WR ref to MT sys clock
# Relax the path where TAI time crosses from WR ref to MT sys clock
# This is already synced via a gc_pulse_synchronizer, which makes sure that
# TAI WR ref value is stable when sampled by the MT sys clock
NET "cmp_mock_turtle/gen_cpus[*].U_CPU_Block/tm_p_sys" TNM_NET = "tm_mt_sync";
TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 16ns DATAPATHONLY;
# Relax timing from spll_aligner outputs cref and cin (driven by ref clock)
# to the spll registers (driven by sys clock). The two sides are already sychronized
# via a gc_pulse_synchronizer, which makes sure that cref and cin are stable
# when sampled by the sys clock.
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cref(*)" TNM_NET = "wr_spll_sync";
NET "*/WRPC/U_SOFTPLL/U_Wrapped_Softpll/aligner_sample_cin(*)" TNM_NET = "wr_spll_sync";
TIMESPEC TS_wr_spll_sync = FROM clk_125m_pllref TO "wr_spll_sync" 16ns DATAPATHONLY;
# External async resets
NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
......
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