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White Rabbit Trigger Distribution
Commit a591946f authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] use SVEC release v1.4.0

parent 7533c4d0
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Showing with 8 additions and 10 deletions
svec @ cf6b2894
Subproject commit 3da89c5c700260ce0d7296438d463d789c44161d
Subproject commit cf6b2894a6c0d3e0b755f73f1310a58074770eda
hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ a591946f
......@@ -35,6 +35,6 @@ except:
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_template_ucf = ['wr', 'led', 'gpio']
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
View file @ a591946f
......@@ -347,7 +347,7 @@ TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
# Cross-clock domain sync
#----------------------------------------
# IMPORTANT: timing constraints are also coming from SVEC template UCF files
# IMPORTANT: timing constraints are also coming from SVEC base UCF files
# Declaration of domains
NET "dcm1_clk_ref_0" TNM_NET = fdl_clk;
......
hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ a591946f
......@@ -34,8 +34,6 @@ modules = {
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
svec_template_ucf = []
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @ a591946f
......@@ -400,16 +400,16 @@ module dut_env
initial begin
// Skip WR SoftPLL lock
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
force DUT.inst_svec_base.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
......
hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
View file @ a591946f
......@@ -495,7 +495,7 @@ begin -- architecture arch
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
inst_svec_template : entity work.svec_template_wr
inst_svec_base : entity work.svec_base_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
......
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