Commit 9de10e18 authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: further restructure and cleanup of dependencies and manifests

parent 8975076d
......@@ -2,10 +2,10 @@
path = dependencies/mock-turtle
url = git://ohwr.org/hdl-core-lib/mock-turtle.git
[submodule "dependencies/fine-delay"]
path = dependencies/fine-delay
path = dependencies/fmc-delay-1ns-8cha
url = git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git
[submodule "dependencies/fmc-tdc"]
path = dependencies/fmc-tdc
path = dependencies/fmc-tdc-1ns-5cha-gw
url = git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git
[submodule "dependencies/vme64x-core"]
path = dependencies/vme64x-core
......@@ -19,6 +19,3 @@
[submodule "dependencies/urv-core"]
path = dependencies/urv-core
url = git://ohwr.org/hdl-core-lib/urv-core.git
[submodule "dependencies/etherbone-core"]
path = dependencies/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
etherbone-core @ f19220ff
Subproject commit f19220ffa3c5e526f66ebbded5e0e1e789e7255d
fine-delay @ 309cd51f
Subproject commit 309cd51f59efc8c10037f220dc22cde73ca9eda9
fmc-delay-1ns-8cha @ 84dca3f5
Subproject commit 84dca3f543664b508445efb56e915275bb02cd19
fmc-tdc @ 8a82e727
Subproject commit 8a82e727483b3e65771c7a36d1371aba24a6db98
fmc-tdc-1ns-5cha-gw @ e8245b04
Subproject commit e8245b04c3ba34869487400ac84b90a746cfd95d
wr-cores @ 02873972
Subproject commit 2573b6cd58732813593e12e3144ff8c87955228c
Subproject commit 02873972e7d9984933ad024e98fe32b88787704e
......@@ -3,6 +3,7 @@
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "svec"
target = "xilinx"
action = "synthesis"
......@@ -13,6 +14,8 @@ syn_top = "svec_list_top"
syn_project = "svec_list_tdc_fd.xise"
syn_tool ="ise"
fetchto = "../../../../dependencies"
syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
......
......@@ -7,14 +7,17 @@ sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
board = "svec"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
fetchto="../../../dependencies"
include_dirs = [
"../../ip_cores/mock-turtle/hdl/testbench/include/",
"../../ip_cores/mock-turtle/hdl/testbench/include/regs/",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/urv-core/rtl/",
fetchto + "/mock-turtle/hdl/testbench/include/",
fetchto + "/mock-turtle/hdl/testbench/include/regs/",
fetchto + "/general-cores/sim/",
fetchto + "/urv-core/rtl/",
]
files = [
......@@ -23,7 +26,7 @@ files = [
]
modules = {
"local" : [
"local" : [
"../../top/svec/list_tdc_fd",
],
}
......@@ -5,17 +5,13 @@ files = [
fetchto = "../../../../dependencies"
modules = {
"local" : [
"../../../ip_cores/wr-cores/board/svec",
"../../../ip_cores/fine-delay/hdl",
"../../../ip_cores/fmc-tdc/hdl/rtl",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git",
"git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git",
],
}
......@@ -47,7 +47,7 @@ use unisim.vcomponents.all;
entity svec_list_top is
generic (
g_DPRAM_INITF : string := "../../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
g_DPRAM_INITF : string := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
......
......@@ -3,7 +3,7 @@
OBJS = rmq-udp.o
OBJS += # add other object files that you need
OUTPUT = fw-rmq-udp
TRTL ?= ../../../hdl/ip_cores/mock-turtle
TRTL ?= ../../../dependencies/mock-turtle
TRTL_SW = $(TRTL)/software
CFLAGS_OPT = -O0 # disable optimization
......
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