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White Rabbit Trigger Distribution
Commit 9b999661 authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch '4-clean-documentation' into 'master' 

doc: replace description of ref designs with a link to the repo

Closes #4

See merge request be-cem-edl/chronos/wrtd!2
parents f0080dac 693d94d2
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doc/Makefile
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......@@ -37,7 +37,7 @@ endif
# List of Doxygen folders to consider
DOXINPUT := ../software/lib
DOXINPUT += ../software/include
DOXINPUT += ../software/firmware/common
DOXINPUT += ../software/firmware/include
DOXEXCL := ""
# List of actual Doxygen source files
......
doc/ref_nodes.rst
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......@@ -7,22 +7,4 @@
Reference Nodes
---------------
WRTD provides so-called "reference" :ref:`Nodes <node>` for the most common use-cases.
Currently these include:
#. :ref:`spec150t_ref_adc`: A four channel, 100MHz, 14bit PCIe-based ADC capable of triggering via
WRTD.
#. :ref:`svec_ref_tdc_fd`: A pulse-in/pulse-out WRTD Node in VME format, for generic trigger
distribution applications.
#. :ref:`svec_ref_tdc_x2`: A pulse-in WRTD Node in VME format.
#. :ref:`svec_ref_fd_x2`: A pulse-out WRTD Node in VME format.
.. toctree::
:hidden:
ref_spec_fmc_adc
ref_svec_tdc_fd
ref_svec_tdc_x2
ref_svec_fd_x2
ref_svec_adc_x2
See repository https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/wrtd-reference-designs for some reference designs.
doc/ref_spec_fmc_adc.rst deleted 100644 → 0
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.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0+
.. _spec150t_ref_adc:
SPEC150T-based FMC-ADC
======================
+----------------------------------------+------------+
| **Parameter** | **Value** |
+========================================+============+
| # of :ref:`Applications <application>` | 1 |
+----------------------------------------+------------+
| Name | wrtd-adc |
+----------------------------------------+------------+
| Local input Channels | 5 |
+----------------------------------------+------------+
| Local output Channels | 1 |
+----------------------------------------+------------+
| Maximum :ref:`Rules <rule>` | 16 |
+----------------------------------------+------------+
| Maximum :ref:`Alarms <alarm>` | 1 |
+----------------------------------------+------------+
| Average input to Message latency | 12μs |
+----------------------------------------+------------+
| Average Message to output latency | 12μs |
+----------------------------------------+------------+
| Can receive Messages over WR | YES |
+----------------------------------------+------------+
| Can send Messages over WR | YES |
+----------------------------------------+------------+
This is a WRTD :ref:`node` based on the `Simple PCIe FMC Carrier (SPEC)
<https://www.ohwr.org/project/spec/wikis/home>`_ and the `FMC ADC 100M 14b 4cha (FMC-ADC)
<https://www.ohwr.org/project/fmc-adc-100m14b4cha/wikis/home>`_.
.. important:: This :ref:`node` does not use the standard SPEC, because the FPGA (XC6SLX45T) is not
large enough for the complete design. Instead it uses the pin-compatible XC6SLX150T
FPGA (the rest of the board is exactly the same, only the FPGA chip is
different). This special version is available from the manufacturers of the SPEC
board upon request.
This :ref:`node` provides the possibility to generate WRTD :ref:`Messages <message>` based on
trigger events of the FMC-ADC, as well as to trigger the FMC-ADC from incoming WRTD :ref:`Messages
<message>`.
.. figure:: graphics/wrtd_ref_design_spec_adc_simple.png
:name: fig-ref_spec_adc
:width: 400pt
:align: center
:alt: alternate text
:figclass: align-center
SPEC150T-based FMC-ADC reference WRTD Node
The architecture of the :ref:`node` can be seen in :numref:`fig-ref_spec_adc`. The user communicates
with the :ref:`node` using one of the methods mentioned in :numref:`usage`. At the same time, the
user accesses the FMC-ADC core to configure everything not related to WRTD (acquisition parameters,
trigger source selection, data retrieval, etc.) using the existing `ADC library
<https://www.ohwr.org/project/adc-lib/wikis/home>`_. Internally, the :ref:`node` is running one
:ref:`application`, responsible for configuring the WRTD-related aspects of the FMC-ADC.
The five :ref:`Local Input Channels <local_channel>` are mapped as follows:
+-------------+---------------------------------+
| **Channel** | **Function** |
+=============+=================================+
| ``LC-I1`` | ADC Channel #1 internal trigger |
+-------------+---------------------------------+
| ``LC-I2`` | ADC Channel #2 internal trigger |
+-------------+---------------------------------+
| ``LC-I3`` | ADC Channel #3 internal trigger |
+-------------+---------------------------------+
| ``LC-I4`` | ADC Channel #4 internal trigger |
+-------------+---------------------------------+
| ``LC-I5`` | External trigger input |
+-------------+---------------------------------+
.. note:: In order for any of the :ref:`Local Input Channels <local_channel>` to produce an
:ref:`event`, the user must also properly configure the trigger source of the FMC-ADC via
the ADC library. This falls outside the scope of WRTD library.
The single :ref:`Local Output Channel <local_channel>` (``LC-O1``) is mapped to the "WRTD" trigger
input of the FMC-ADC.
.. note:: In order for :ref:`Local Output Channel <local_channel>` to trigger the FMC-ADC, the user
must also properly configure the trigger source of the FMC-ADC via the ADC library, to
enable triggering from the "WRTD" trigger input. This falls outside the scope of WRTD
library.
.. hint:: The User Application and the WRTD Application access different and separate parts of the
FMC-ADC, so there is no danger of accessing the same resources simultaneously.
doc/ref_svec_adc_x2.rst deleted 100644 → 0
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.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0+
.. _svec_ref_adc_x2:
SVEC-based ADC x 2
==================
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_ and the `FMC ADC 100M 14b 4cha (FMC-ADC)
<https://www.ohwr.org/project/fmc-adc-100m14b4cha/wikis/home>`_.
This :ref:`node` provides the possibility to generate WRTD :ref:`Messages <message>` based on
trigger events of the FMC-ADC, as well as to trigger the FMC-ADC from incoming WRTD :ref:`Messages
<message>`.
The node has 10 :ref:`Local Input Channels <local_channel>`. Channels 1 to 4
are mapped to the internal trigger of adc #1, channel 5 to the external trigger
input of adc #1, channels 6 to 9 to the intern triggers of adc #2 and
channel 10 to the external trigger input of adc #2.
doc/ref_svec_fd_x2.rst deleted 100644 → 0
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.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0+
.. _svec_ref_fd_x2:
SVEC-based FD x 2
=================
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_ and the `FMC Fine Delay generator
(FMC-FD) <https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/home>`_.
The basic principle of this :ref:`node` is simple: the :ref:`node`
also receives WRTD :ref:`Messages <message>` which are then used to
generate pulses at a predefined moment on one of the FMC-FD outputs.
Architecture and performances are similar to :ref:`svec_ref_tdc_fd`.
The node has 10 :ref:`Local Output Channels <local_channel>`, they are
mapped to the five inputs of each FMC-FD.
doc/ref_svec_tdc_fd.rst deleted 100644 → 0
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.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0+
.. _svec_ref_tdc_fd:
SVEC-based TDC+FD
=================
+----------------------------------------+------------+------------+
| **Parameter** | **Value** |
+========================================+============+============+
| # of :ref:`Applications <application>` | 2 |
+----------------------------------------+------------+------------+
| | **App #1** | **App #2** |
+----------------------------------------+------------+------------+
| Name | wrtd-tdc | wrtd-fd |
+----------------------------------------+------------+------------+
| Local input Channels | 5 | 0 |
+----------------------------------------+------------+------------+
| Local output Channels | 0 | 4 |
+----------------------------------------+------------+------------+
| Maximum :ref:`Rules <rule>` | 16 | 16 |
+----------------------------------------+------------+------------+
| Maximum :ref:`Alarms <alarm>` | 0 | 1 |
+----------------------------------------+------------+------------+
| Average input to Message latency | 20μs | N.A. |
+----------------------------------------+------------+------------+
| Average Message to output latency | N.A. | 20μs |
+----------------------------------------+------------+------------+
| Can receive Messages over WR | NO | YES |
+----------------------------------------+------------+------------+
| Can send Messages over WR | YES | NO |
+----------------------------------------+------------+------------+
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_, the `FMC Time to Digital Converter (FMC-TDC)
<https://www.ohwr.org/project/fmc-tdc/wikis/home>`_ and the `FMC Fine Delay generator (FMC-FD)
<https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/home>`_.
.. important:: The FMC-TDC should always be attached to "FMC Slot 1" of the SVEC, and the FMC-FD
should always be attached to "FMC Slot 2". It is not necessary though to have both
the FMCs attached, the :ref:`Node` will work if only one of the two (TDC or FD) is
present, as long as it is connected to the correct FMC slot.
The basic principle of this :ref:`node` is simple: it takes in external pulses on its FMC-TDC
inputs, timestamps them using WR time and converts them to WRTD :ref:`Messages <message>`, to be
sent over the WR network. Conversely, the :ref:`node` also receives WRTD :ref:`Messages <message>`
which are then used to generate pulses at a predefined moment on one of the FMC-FD outputs. As such,
it can be seen as a "pulse-to-message" and "message-to-pulse" converter with apllications in the
fields of pulse distribution, trigger synchronisation, etc.
.. figure:: graphics/wrtd_ref_design_svec_list_simple.png
:name: fig-ref_svec_list
:width: 400pt
:align: center
:alt: alternate text
:figclass: align-center
SVEC-based TDC+FD reference WRTD Node
The architecture of the :ref:`node` can be seen in :numref:`fig-ref_svec_list`. The user
communicates with the :ref:`node` via the WRTD library, using one of the methods mentioned in
:numref:`usage`. Internally, the :ref:`node` is running two :ref:`Applications <application>`, each
on a dedicated CPU. One is responsible for the FMC-TDC peripheral, while the other handles the
FMC-FD.
The five :ref:`Local Input Channels <local_channel>` are mapped to the five inputs of the
FMC-TDC. Thus, :ref:`event_id` ``LC-I1`` corresponds to the first FMC-TDC channel, ``LC-I2`` to the
second one, and so on, up to ``LC-I5``.
The four :ref:`Local Output Channels <local_channel>` are mapped to the four outputs of the
FMC-FD. :ref:`event_id` ``LC-O1`` corresponds to the first FMC-FD output, and so on, up to
``LC-O4``.
.. hint:: It is possible for the User Application in :numref:`fig-ref_svec_list` to access directly
the FMC-TDC and FMC-FD cores by means of their respective libraries (shown in
:numref:`fig-ref_svec_list` with dotted lines), in order to fine-tune them and/or change
their default behaviour. However this should be done with extreme care, as it could lead
to a race condition between the User Application and the WRTD Applications running inside
the FPGA.
The front-panel LEMO connectors of the SVEC are used as follows:
+---------------+-----------------------------------+
| **Connector** | **Function** |
+===============+===================================+
| L1 | WR 1-PPS output |
+---------------+-----------------------------------+
| L2 | Not used |
+---------------+-----------------------------------+
| L3 | WR external reference clock input |
+---------------+-----------------------------------+
| L4 | WR external 1-PPS input |
+---------------+-----------------------------------+
The front-panel LED indicators have the following meanings:
+---------------------------+----+----+----------------------------+
| **Function** | **LED** | **Function** |
+===========================+====+====+============================+
| WR link activity | 4 | 8 | WR link up |
+---------------------------+----+----+----------------------------+
| FMC-FD clock locked to WR | 3 | 7 | FMC-TDC clock locked to WR |
+---------------------------+----+----+----------------------------+
| WR locked | 2 | 6 | Not used |
+---------------------------+----+----+----------------------------+
| VME bus access | 1 | 5 | WR 1-PPS |
+---------------------------+----+----+----------------------------+
.. hint:: LED colors follow a certain convention:
* A green LED means ``OK`` or ``on``.
* A LED that is turned off means ``off`` or ``not active``.
* A red LED means ``error``.
* An orange LED signifies ``activity`` (used by LEDs 1, 4 and 5).
doc/ref_svec_tdc_x2.rst deleted 100644 → 0
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.. Copyright (c) 2019 CERN (home.cern)
SPDX-License-Identifier: CC-BY-SA-4.0+
.. _svec_ref_tdc_x2:
SVEC-based TDC x 2
==================
This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_ and the `FMC Time to Digital Converter (FMC-TDC)
<https://www.ohwr.org/project/fmc-tdc/wikis/home>`_.
The basic principle of this :ref:`node` is simple: it takes in
external pulses on its FMC-TDC inputs, timestamps them using WR time
and converts them to WRTD :ref:`Messages <message>`, to be sent over
the WR network.
Architecture and performances are similar to :ref:`svec_ref_tdc_fd`.
The node has 10 :ref:`Local Input Channels <local_channel>`, they are mapped
to the five inputs of each FMC-TDC.
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