Commit 91db04c0 authored by Tristan Gingold's avatar Tristan Gingold

Adjust builder for svec_adc.

parent a6d319ce
......@@ -98,9 +98,9 @@ use work.ddr3_ctrl_pkg.all;
name => "WB-DDR-Addr-Access ")));
[sdb-layout]
c_WB_SLAVE_FMC{n}_ADC => f_sdb_embed_bridge(c_FMC{n}_BRIDGE_SDB, x"{addr}"),
c_WB_SLAVE_FMC{n}_DDR_ADR => f_sdb_embed_device(c_WB_DDR{n}_ADR_SDB, x"{addr}" or x"4000"),
c_WB_SLAVE_FMC{n}_DDR_DAT => f_sdb_embed_device(c_WB_DDR{n}_DAT_SDB, x"{addr}" or x"5000"),
c_WB_SLAVE_FMC{n}_ADC => f_sdb_embed_bridge(c_FMC{n}_BRIDGE_SDB, x"{addr}" or x"2000"),
c_WB_SLAVE_FMC{n}_DDR_ADR => f_sdb_embed_device(c_WB_DDR{n}_ADR_SDB, x"{addr}" or x"4000"),
c_WB_SLAVE_FMC{n}_DDR_DAT => f_sdb_embed_device(c_WB_DDR{n}_DAT_SDB, x"{addr}" or x"5000"),
[decls]
constant g_FMC{n}_MULTISHOT_RAM_SIZE : natural := 2048;
......@@ -276,7 +276,7 @@ use work.ddr3_ctrl_pkg.all;
cmp_ddr{n}_ctrl_bank : ddr3_ctrl
generic map (
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_RST_ACT_LOW => 1, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => f_ddr{n}_bank_sel,
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_FMC{n}_SIMULATION_STR,
......
......@@ -44,6 +44,7 @@ use work.wr_board_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.ddr3_ctrl_pkg.all;
entity svec_adc_top is
generic (
g_WR_DPRAM_INITF : string := "../../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
......@@ -333,12 +334,9 @@ architecture arch of svec_adc_top is
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"),
c_WB_SLAVE_FMC0_ADC => f_sdb_embed_bridge(c_FMC0_BRIDGE_SDB,
x"00010000" or x"2000"),
c_WB_SLAVE_FMC0_DDR_ADR => f_sdb_embed_device(c_WB_DDR0_ADR_SDB,
x"00010000" or x"4000"),
c_WB_SLAVE_FMC0_DDR_DAT => f_sdb_embed_device(c_WB_DDR0_DAT_SDB,
x"00010000" or x"5000"),
c_WB_SLAVE_FMC0_ADC => f_sdb_embed_bridge(c_FMC0_BRIDGE_SDB, x"00010000" or x"2000"),
c_WB_SLAVE_FMC0_DDR_ADR => f_sdb_embed_device(c_WB_DDR0_ADR_SDB, x"00010000" or x"4000"),
c_WB_SLAVE_FMC0_DDR_DAT => f_sdb_embed_device(c_WB_DDR0_DAT_SDB, x"00010000" or x"5000"),
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"),
......@@ -359,7 +357,7 @@ architecture arch of svec_adc_top is
constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
(0 => x"10000000");
constant c_mt_config : t_mt_config :=
(
app_id => x"115790d1",
......@@ -1148,6 +1146,7 @@ begin -- architecture arch
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).rty <= '0';
cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).stall <= '0';
-- Note: g_address/g_mask index direction is to, master_i/master_o is downto
cpu0_crossbar : xwb_crossbar
generic map (
g_num_masters => 1,
......@@ -1164,7 +1163,7 @@ begin -- architecture arch
slave_o(0) => fmc_dp_wb_in(0),
master_i(1) => wb_adc0_trigout_slave_out,
master_i(0) => wb_adc0_trigin_slave_out,
master_o(1) => wb_adc0_trigout_slave_in);
master_o(1) => wb_adc0_trigout_slave_in,
master_o(0) => wb_adc0_trigin_slave_in);
......
......@@ -43,9 +43,6 @@ use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
{use}
library unisim;
use unisim.vcomponents.all;
entity {name}_top is
generic (
g_WR_DPRAM_INITF : string := "{topdir}/wr-cores/bin/wrpc/wrc_phy8.bram";
......
......@@ -151,6 +151,7 @@ def generate_cpu_xbar_hdl(f, templates):
templates['body'] += txt
else:
txt = """
-- Note: g_address/g_mask index direction is to, master_i/master_o is downto
cpu{}_crossbar : xwb_crossbar
generic map (
g_num_masters => 1,
......@@ -166,9 +167,9 @@ def generate_cpu_xbar_hdl(f, templates):
rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out({}),
slave_o(0) => fmc_dp_wb_in({})""".format(k, k)
for s in range(len(slaves)):
for s in reversed(range(len(slaves))):
txt += ',\n master_i({}) => {}_out'.format(s, slaves[s])
for s in range(len(slaves)):
for s in reversed(range(len(slaves))):
txt += ',\n master_o({}) => {}_in'.format(s, slaves[s])
txt += ");\n"
templates['body'] += txt
......@@ -301,7 +302,7 @@ def main():
res.ncpus = len(res.cpus)
build_mt_config(desc, res)
res.slots = {k: Slot(v, k) for k, v in desc['slots'].items()}
# Get the slots index for the board.
res.board = desc['board']
board_slots = BOARD_SLOTS.get(res.board, None)
......
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