Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit Trigger Distribution
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit Trigger Distribution
Commits
806a5591
Commit
806a5591
authored
Oct 20, 2021
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Plain Diff
CI implementation by Konstantinos Blantos
See merge request
!5
parents
f7f79c41
c1a31252
Pipeline
#2734
passed with stages
in 47 minutes and 34 seconds
Changes
2
Pipelines
1
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
110 additions
and
4 deletions
+110
-4
.gitlab-ci.yml
.gitlab-ci.yml
+107
-0
dut_env.sv
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
+3
-4
No files found.
.gitlab-ci.yml
0 → 100644
View file @
806a5591
variables
:
GIT_SUBMODULE_STRATEGY
:
normal
GIT_DEPTH
:
"
1"
stages
:
-
simulation
-
build
SPEC150T-ADC simulate
:
tags
:
-
questasim_105c
# only:
# - schedules
stage
:
simulation
script
:
-
/entrypoint.sh
-
echo "Starting SPEC150T-ADC simulate!"
-
export TMP_DIR=$(mktemp -d)
-
export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
-
curl $PAK | tar xJ -C $TMP_DIR
-
export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
-
cd hdl/testbench/wrtd_ref_spec150t_adc/
-
source ~/setup_questasim.sh
-
git submodule init && git submodule update
-
cp /opt/compiled_libs_ise14.7/modelsim.ini .
-
hdlmake makefile
-
make
-
vsim -c -do run.do
artifacts
:
paths
:
-
hdl/testbench/wrtd_ref_spec150t_adc/transcript
SPEC150T-ADC build
:
tags
:
-
ise_14.7
# only:
# - schedules
stage
:
build
script
:
-
/entrypoint.sh
-
echo "Starting SPEC150T-ADC build!"
-
export TMP_DIR=$(mktemp -d)
-
export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
-
curl $PAK | tar xJ -C $TMP_DIR
-
export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
-
cd hdl/syn/wrtd_ref_spec150t_adc/
-
source ~/setup_ise147.sh
-
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-
hdlmake makefile
-
make
-
git rev-parse HEAD | cut -c 1-8
artifacts
:
name
:
"
$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
paths
:
-
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.syr
-
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.par
-
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.twr
-
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.bit
-
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.bin
SVEC-TDC-FD simulate
:
tags
:
-
questasim_105c
# only:
# - schedules
stage
:
simulation
script
:
-
/entrypoint.sh
-
echo "Starting SVEC-TDC-FD simulation!"
-
export TMP_DIR=$(mktemp -d)
-
export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
-
curl $PAK | tar xJ -C $TMP_DIR
-
export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
-
cd hdl/testbench/wrtd_ref_svec_tdc_fd/
-
source ~/setup_questasim.sh
-
cp /opt/compiled_libs_ise14.7/modelsim.ini .
-
hdlmake makefile
-
make
-
vsim -c -do run_ci.do
artifacts
:
paths
:
-
hdl/testbench/wrtd_ref_svec_tdc_fd/transcript
SVEC-TDC-FD build
:
tags
:
-
ise_14.7
stage
:
build
script
:
-
/entrypoint.sh
-
echo "Starting SVEC-TDC-FD build!"
-
export TMP_DIR=$(mktemp -d)
-
export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
-
curl $PAK | tar xJ -C $TMP_DIR
-
export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
-
cd hdl/syn/wrtd_ref_svec_tdc_fd/
-
source ~/setup_ise147.sh
-
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-
hdlmake makefile
-
make
-
git rev-parse HEAD | cut -c 1-8
artifacts
:
paths
:
-
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.syr
-
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.par
-
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.twr
-
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.bit
-
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.bin
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @
806a5591
...
...
@@ -74,8 +74,7 @@ module simple_tdc_driver
acam_fifo_entry
t
;
time
now
;
wait
(
pulses
.
size
()
!=
0
)
;
wait
(
pulses
.
size
()
!=
0
)
;
t
=
pulses
.
pop_front
()
;
now
=
$
time
;
...
...
@@ -103,7 +102,7 @@ module simple_tdc_driver
val
[
27
:
26
]
=
t
.
channel
&
2'b11
;
val
[
25
:
18
]
=
start
;
val
[
17
]
=
1'b0
;
val
[
16
:
0
]
=
(
t
.
duration
+
t
.
ts
-
start_time
)
/
81
ps
;
val
[
16
:
0
]
=
(
t
.
duration
+
t
.
ts
-
start_time
)
/
81.0
ps
;
fifos
[
t
.
channel
/
4
]
.
push_back
(
val
)
;
...
...
@@ -127,7 +126,7 @@ module simple_tdc_driver
if
(
restart_pulse
)
begin
start
=
1
;
restart_pulse
=
0
;
start01
=
($
time
-
restart_time
)
/
81
ps
;
start01
=
($
time
-
restart_time
)
/
81.0
ps
;
end
else
begin
start_time
=
$
time
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment